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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P56003--- |4 5 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>)6 define void @add_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }7 8 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>)9 define void @add_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }10 11 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>)12 define void @add_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }13 14 declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>)15 define void @add_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }16 17 declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32 immarg)18 define void @add_v16i8_builtin_imm(ptr %a, ptr %c) { entry: ret void }19 20 declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32 immarg)21 define void @add_v8i16_builtin_imm(ptr %a, ptr %c) { entry: ret void }22 23 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)24 define void @add_v4i32_builtin_imm(ptr %a, ptr %c) { entry: ret void }25 26 declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32 immarg)27 define void @add_v2i64_builtin_imm(ptr %a, ptr %c) { entry: ret void }28 29...30---31name: add_v16i8_builtin32alignment: 433tracksRegLiveness: true34body: |35 bb.1.entry:36 liveins: $a0, $a1, $a237 38 ; P5600-LABEL: name: add_v16i8_builtin39 ; P5600: liveins: $a0, $a1, $a240 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a041 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a142 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a243 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)44 ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)45 ; P5600: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[LOAD]], [[LOAD1]]46 ; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)47 ; P5600: RetRA48 %0:_(p0) = COPY $a049 %1:_(p0) = COPY $a150 %2:_(p0) = COPY $a251 %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)52 %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)53 %5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addv.b), %3(<16 x s8>), %4(<16 x s8>)54 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)55 RetRA56 57...58---59name: add_v8i16_builtin60alignment: 461tracksRegLiveness: true62body: |63 bb.1.entry:64 liveins: $a0, $a1, $a265 66 ; P5600-LABEL: name: add_v8i16_builtin67 ; P5600: liveins: $a0, $a1, $a268 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a069 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a170 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a271 ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)72 ; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)73 ; P5600: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[LOAD]], [[LOAD1]]74 ; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)75 ; P5600: RetRA76 %0:_(p0) = COPY $a077 %1:_(p0) = COPY $a178 %2:_(p0) = COPY $a279 %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)80 %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)81 %5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addv.h), %3(<8 x s16>), %4(<8 x s16>)82 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)83 RetRA84 85...86---87name: add_v4i32_builtin88alignment: 489tracksRegLiveness: true90body: |91 bb.1.entry:92 liveins: $a0, $a1, $a293 94 ; P5600-LABEL: name: add_v4i32_builtin95 ; P5600: liveins: $a0, $a1, $a296 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a097 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a198 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a299 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)100 ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)101 ; P5600: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[LOAD]], [[LOAD1]]102 ; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)103 ; P5600: RetRA104 %0:_(p0) = COPY $a0105 %1:_(p0) = COPY $a1106 %2:_(p0) = COPY $a2107 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)108 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)109 %5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addv.w), %3(<4 x s32>), %4(<4 x s32>)110 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)111 RetRA112 113...114---115name: add_v2i64_builtin116alignment: 4117tracksRegLiveness: true118body: |119 bb.1.entry:120 liveins: $a0, $a1, $a2121 122 ; P5600-LABEL: name: add_v2i64_builtin123 ; P5600: liveins: $a0, $a1, $a2124 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0125 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1126 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2127 ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)128 ; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)129 ; P5600: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[LOAD]], [[LOAD1]]130 ; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)131 ; P5600: RetRA132 %0:_(p0) = COPY $a0133 %1:_(p0) = COPY $a1134 %2:_(p0) = COPY $a2135 %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)136 %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)137 %5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addv.d), %3(<2 x s64>), %4(<2 x s64>)138 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)139 RetRA140 141...142---143name: add_v16i8_builtin_imm144alignment: 4145tracksRegLiveness: true146body: |147 bb.1.entry:148 liveins: $a0, $a1149 150 ; P5600-LABEL: name: add_v16i8_builtin_imm151 ; P5600: liveins: $a0, $a1152 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0153 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1154 ; P5600: [[LOAD:%[0-9]+]]:msa128b(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)155 ; P5600: [[ADDVI_B:%[0-9]+]]:msa128b(<16 x s8>) = ADDVI_B [[LOAD]](<16 x s8>), 3156 ; P5600: G_STORE [[ADDVI_B]](<16 x s8>), [[COPY1]](p0) :: (store (<16 x s8>) into %ir.c)157 ; P5600: RetRA158 %0:_(p0) = COPY $a0159 %1:_(p0) = COPY $a1160 %2:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)161 %3:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.b), %2(<16 x s8>), 3162 G_STORE %3(<16 x s8>), %1(p0) :: (store (<16 x s8>) into %ir.c)163 RetRA164 165...166---167name: add_v8i16_builtin_imm168alignment: 4169tracksRegLiveness: true170body: |171 bb.1.entry:172 liveins: $a0, $a1173 174 ; P5600-LABEL: name: add_v8i16_builtin_imm175 ; P5600: liveins: $a0, $a1176 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0177 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1178 ; P5600: [[LOAD:%[0-9]+]]:msa128h(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)179 ; P5600: [[ADDVI_H:%[0-9]+]]:msa128h(<8 x s16>) = ADDVI_H [[LOAD]](<8 x s16>), 18180 ; P5600: G_STORE [[ADDVI_H]](<8 x s16>), [[COPY1]](p0) :: (store (<8 x s16>) into %ir.c)181 ; P5600: RetRA182 %0:_(p0) = COPY $a0183 %1:_(p0) = COPY $a1184 %2:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)185 %3:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.h), %2(<8 x s16>), 18186 G_STORE %3(<8 x s16>), %1(p0) :: (store (<8 x s16>) into %ir.c)187 RetRA188 189...190---191name: add_v4i32_builtin_imm192alignment: 4193tracksRegLiveness: true194body: |195 bb.1.entry:196 liveins: $a0, $a1197 198 ; P5600-LABEL: name: add_v4i32_builtin_imm199 ; P5600: liveins: $a0, $a1200 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0201 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1202 ; P5600: [[LOAD:%[0-9]+]]:msa128w(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)203 ; P5600: [[ADDVI_W:%[0-9]+]]:msa128w(<4 x s32>) = ADDVI_W [[LOAD]](<4 x s32>), 25204 ; P5600: G_STORE [[ADDVI_W]](<4 x s32>), [[COPY1]](p0) :: (store (<4 x s32>) into %ir.c)205 ; P5600: RetRA206 %0:_(p0) = COPY $a0207 %1:_(p0) = COPY $a1208 %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)209 %3:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.w), %2(<4 x s32>), 25210 G_STORE %3(<4 x s32>), %1(p0) :: (store (<4 x s32>) into %ir.c)211 RetRA212 213...214---215name: add_v2i64_builtin_imm216alignment: 4217tracksRegLiveness: true218body: |219 bb.1.entry:220 liveins: $a0, $a1221 222 ; P5600-LABEL: name: add_v2i64_builtin_imm223 ; P5600: liveins: $a0, $a1224 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0225 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1226 ; P5600: [[LOAD:%[0-9]+]]:msa128d(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)227 ; P5600: [[ADDVI_D:%[0-9]+]]:msa128d(<2 x s64>) = ADDVI_D [[LOAD]](<2 x s64>), 31228 ; P5600: G_STORE [[ADDVI_D]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.c)229 ; P5600: RetRA230 %0:_(p0) = COPY $a0231 %1:_(p0) = COPY $a1232 %2:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)233 %3:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.addvi.d), %2(<2 x s64>), 31234 G_STORE %3(<2 x s64>), %1(p0) :: (store (<2 x s64>) into %ir.c)235 RetRA236 237...238