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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS323--- |4 5 define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}6 define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void}7 define void @load1_s8_to_zextLoad1_s16(ptr %px) {entry: ret void}8 define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(ptr %px) {entry: ret void}9 define void @load4_s32_to_zextLoad4_s64(ptr %px) {entry: ret void}10 define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}11 define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}12 define void @load1_s8_to_sextLoad1_s16(ptr %px) {entry: ret void}13 define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(ptr %px) {entry: ret void}14 define void @load4_s32_to_sextLoad4_s64(ptr %px) {entry: ret void}15 16...17---18name: load1_s8_to_zextLoad1_s3219alignment: 420tracksRegLiveness: true21body: |22 bb.1.entry:23 liveins: $a024 25 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s3226 ; MIPS32: liveins: $a027 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a028 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)29 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)30 ; MIPS32: RetRA implicit $v031 %0:_(p0) = COPY $a032 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)33 $v0 = COPY %2(s32)34 RetRA implicit $v035 36...37---38name: load2_s16_to_zextLoad2_s3239alignment: 440tracksRegLiveness: true41body: |42 bb.1.entry:43 liveins: $a044 45 ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s3246 ; MIPS32: liveins: $a047 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a048 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)49 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)50 ; MIPS32: RetRA implicit $v051 %0:_(p0) = COPY $a052 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)53 $v0 = COPY %2(s32)54 RetRA implicit $v055 56...57---58name: load1_s8_to_zextLoad1_s1659alignment: 460tracksRegLiveness: true61body: |62 bb.1.entry:63 liveins: $a064 65 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s1666 ; MIPS32: liveins: $a067 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a068 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)69 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)70 ; MIPS32: RetRA implicit $v071 %0:_(p0) = COPY $a072 %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)73 %3:_(s32) = G_ANYEXT %2(s16)74 $v0 = COPY %3(s32)75 RetRA implicit $v076 77...78---79name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s3280alignment: 481tracksRegLiveness: true82body: |83 bb.1.entry:84 liveins: $a085 86 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s3287 ; MIPS32: liveins: $a088 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a089 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)90 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)91 ; MIPS32: RetRA implicit $v092 %0:_(p0) = COPY $a093 %3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)94 $v0 = COPY %3(s32)95 RetRA implicit $v096 97...98---99name: load4_s32_to_zextLoad4_s64100alignment: 4101tracksRegLiveness: true102body: |103 bb.1.entry:104 liveins: $a0105 106 ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64107 ; MIPS32: liveins: $a0108 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0109 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)110 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0111 ; MIPS32: $v0 = COPY [[LOAD]](s32)112 ; MIPS32: $v1 = COPY [[C]](s32)113 ; MIPS32: RetRA implicit $v0, implicit $v1114 %0:_(p0) = COPY $a0115 %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32) from %ir.px)116 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)117 $v0 = COPY %3(s32)118 $v1 = COPY %4(s32)119 RetRA implicit $v0, implicit $v1120 121...122---123name: load1_s8_to_sextLoad1_s32124alignment: 4125tracksRegLiveness: true126body: |127 bb.1.entry:128 liveins: $a0129 130 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32131 ; MIPS32: liveins: $a0132 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0133 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)134 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)135 ; MIPS32: RetRA implicit $v0136 %0:_(p0) = COPY $a0137 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)138 $v0 = COPY %2(s32)139 RetRA implicit $v0140 141...142---143name: load2_s16_to_sextLoad2_s32144alignment: 4145tracksRegLiveness: true146body: |147 bb.1.entry:148 liveins: $a0149 150 ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32151 ; MIPS32: liveins: $a0152 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0153 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)154 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)155 ; MIPS32: RetRA implicit $v0156 %0:_(p0) = COPY $a0157 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)158 $v0 = COPY %2(s32)159 RetRA implicit $v0160 161...162---163name: load1_s8_to_sextLoad1_s16164alignment: 4165tracksRegLiveness: true166body: |167 bb.1.entry:168 liveins: $a0169 170 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16171 ; MIPS32: liveins: $a0172 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0173 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)174 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)175 ; MIPS32: RetRA implicit $v0176 %0:_(p0) = COPY $a0177 %2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)178 %3:_(s32) = G_ANYEXT %2(s16)179 $v0 = COPY %3(s32)180 RetRA implicit $v0181 182...183---184name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32185alignment: 4186tracksRegLiveness: true187body: |188 bb.1.entry:189 liveins: $a0190 191 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32192 ; MIPS32: liveins: $a0193 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0194 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)195 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)196 ; MIPS32: RetRA implicit $v0197 %0:_(p0) = COPY $a0198 %3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)199 $v0 = COPY %3(s32)200 RetRA implicit $v0201 202...203---204name: load4_s32_to_sextLoad4_s64205alignment: 4206tracksRegLiveness: true207body: |208 bb.1.entry:209 liveins: $a0210 211 ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64212 ; MIPS32: liveins: $a0213 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0214 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)215 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31216 ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)217 ; MIPS32: $v0 = COPY [[LOAD]](s32)218 ; MIPS32: $v1 = COPY [[ASHR]](s32)219 ; MIPS32: RetRA implicit $v0, implicit $v1220 %0:_(p0) = COPY $a0221 %2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32) from %ir.px)222 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)223 $v0 = COPY %3(s32)224 $v1 = COPY %4(s32)225 RetRA implicit $v0, implicit $v1226 227...228