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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P56003 4declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>)5define void @mul_v16i8_builtin(ptr %a, ptr %b, ptr %c) {6; P5600-LABEL: mul_v16i8_builtin:7; P5600: # %bb.0: # %entry8; P5600-NEXT: ld.b $w0, 0($4)9; P5600-NEXT: ld.b $w1, 0($5)10; P5600-NEXT: mulv.b $w0, $w0, $w111; P5600-NEXT: st.b $w0, 0($6)12; P5600-NEXT: jr $ra13; P5600-NEXT: nop14entry:15 %0 = load <16 x i8>, ptr %a, align 1616 %1 = load <16 x i8>, ptr %b, align 1617 %2 = tail call <16 x i8> @llvm.mips.mulv.b(<16 x i8> %0, <16 x i8> %1)18 store <16 x i8> %2, ptr %c, align 1619 ret void20}21 22declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>)23define void @mul_v8i16_builtin(ptr %a, ptr %b, ptr %c) {24; P5600-LABEL: mul_v8i16_builtin:25; P5600: # %bb.0: # %entry26; P5600-NEXT: ld.h $w0, 0($4)27; P5600-NEXT: ld.h $w1, 0($5)28; P5600-NEXT: mulv.h $w0, $w0, $w129; P5600-NEXT: st.h $w0, 0($6)30; P5600-NEXT: jr $ra31; P5600-NEXT: nop32entry:33 %0 = load <8 x i16>, ptr %a, align 1634 %1 = load <8 x i16>, ptr %b, align 1635 %2 = tail call <8 x i16> @llvm.mips.mulv.h(<8 x i16> %0, <8 x i16> %1)36 store <8 x i16> %2, ptr %c, align 1637 ret void38}39 40declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>)41define void @mul_v4i32_builtin(ptr %a, ptr %b, ptr %c) {42; P5600-LABEL: mul_v4i32_builtin:43; P5600: # %bb.0: # %entry44; P5600-NEXT: ld.w $w0, 0($4)45; P5600-NEXT: ld.w $w1, 0($5)46; P5600-NEXT: mulv.w $w0, $w0, $w147; P5600-NEXT: st.w $w0, 0($6)48; P5600-NEXT: jr $ra49; P5600-NEXT: nop50entry:51 %0 = load <4 x i32>, ptr %a, align 1652 %1 = load <4 x i32>, ptr %b, align 1653 %2 = tail call <4 x i32> @llvm.mips.mulv.w(<4 x i32> %0, <4 x i32> %1)54 store <4 x i32> %2, ptr %c, align 1655 ret void56}57 58declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>)59define void @mul_v2i64_builtin(ptr %a, ptr %b, ptr %c) {60; P5600-LABEL: mul_v2i64_builtin:61; P5600: # %bb.0: # %entry62; P5600-NEXT: ld.d $w0, 0($4)63; P5600-NEXT: ld.d $w1, 0($5)64; P5600-NEXT: mulv.d $w0, $w0, $w165; P5600-NEXT: st.d $w0, 0($6)66; P5600-NEXT: jr $ra67; P5600-NEXT: nop68entry:69 %0 = load <2 x i64>, ptr %a, align 1670 %1 = load <2 x i64>, ptr %b, align 1671 %2 = tail call <2 x i64> @llvm.mips.mulv.d(<2 x i64> %0, <2 x i64> %1)72 store <2 x i64> %2, ptr %c, align 1673 ret void74}75