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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P56003 4declare <16 x i8> @llvm.mips.subv.b(<16 x i8>, <16 x i8>)5define void @sub_v16i8_builtin(ptr %a, ptr %b, ptr %c) {6; P5600-LABEL: sub_v16i8_builtin:7; P5600: # %bb.0: # %entry8; P5600-NEXT: ld.b $w0, 0($4)9; P5600-NEXT: ld.b $w1, 0($5)10; P5600-NEXT: subv.b $w0, $w0, $w111; P5600-NEXT: st.b $w0, 0($6)12; P5600-NEXT: jr $ra13; P5600-NEXT: nop14entry:15 %0 = load <16 x i8>, ptr %a, align 1616 %1 = load <16 x i8>, ptr %b, align 1617 %2 = tail call <16 x i8> @llvm.mips.subv.b(<16 x i8> %0, <16 x i8> %1)18 store <16 x i8> %2, ptr %c, align 1619 ret void20}21 22declare <8 x i16> @llvm.mips.subv.h(<8 x i16>, <8 x i16>)23define void @sub_v8i16_builtin(ptr %a, ptr %b, ptr %c) {24; P5600-LABEL: sub_v8i16_builtin:25; P5600: # %bb.0: # %entry26; P5600-NEXT: ld.h $w0, 0($4)27; P5600-NEXT: ld.h $w1, 0($5)28; P5600-NEXT: subv.h $w0, $w0, $w129; P5600-NEXT: st.h $w0, 0($6)30; P5600-NEXT: jr $ra31; P5600-NEXT: nop32entry:33 %0 = load <8 x i16>, ptr %a, align 1634 %1 = load <8 x i16>, ptr %b, align 1635 %2 = tail call <8 x i16> @llvm.mips.subv.h(<8 x i16> %0, <8 x i16> %1)36 store <8 x i16> %2, ptr %c, align 1637 ret void38}39 40declare <4 x i32> @llvm.mips.subv.w(<4 x i32>, <4 x i32>)41define void @sub_v4i32_builtin(ptr %a, ptr %b, ptr %c) {42; P5600-LABEL: sub_v4i32_builtin:43; P5600: # %bb.0: # %entry44; P5600-NEXT: ld.w $w0, 0($4)45; P5600-NEXT: ld.w $w1, 0($5)46; P5600-NEXT: subv.w $w0, $w0, $w147; P5600-NEXT: st.w $w0, 0($6)48; P5600-NEXT: jr $ra49; P5600-NEXT: nop50entry:51 %0 = load <4 x i32>, ptr %a, align 1652 %1 = load <4 x i32>, ptr %b, align 1653 %2 = tail call <4 x i32> @llvm.mips.subv.w(<4 x i32> %0, <4 x i32> %1)54 store <4 x i32> %2, ptr %c, align 1655 ret void56}57 58declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>)59define void @sub_v2i64_builtin(ptr %a, ptr %b, ptr %c) {60; P5600-LABEL: sub_v2i64_builtin:61; P5600: # %bb.0: # %entry62; P5600-NEXT: ld.d $w0, 0($4)63; P5600-NEXT: ld.d $w1, 0($5)64; P5600-NEXT: subv.d $w0, $w0, $w165; P5600-NEXT: st.d $w0, 0($6)66; P5600-NEXT: jr $ra67; P5600-NEXT: nop68entry:69 %0 = load <2 x i64>, ptr %a, align 1670 %1 = load <2 x i64>, ptr %b, align 1671 %2 = tail call <2 x i64> @llvm.mips.subv.d(<2 x i64> %0, <2 x i64> %1)72 store <2 x i64> %2, ptr %c, align 1673 ret void74}75 76declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32 immarg)77define void @sub_v16i8_builtin_imm(ptr %a, ptr %c) {78; P5600-LABEL: sub_v16i8_builtin_imm:79; P5600: # %bb.0: # %entry80; P5600-NEXT: ld.b $w0, 0($4)81; P5600-NEXT: subvi.b $w0, $w0, 382; P5600-NEXT: st.b $w0, 0($5)83; P5600-NEXT: jr $ra84; P5600-NEXT: nop85entry:86 %0 = load <16 x i8>, ptr %a, align 1687 %1 = tail call <16 x i8> @llvm.mips.subvi.b(<16 x i8> %0, i32 3)88 store <16 x i8> %1, ptr %c, align 1689 ret void90}91 92declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32 immarg)93define void @sub_v8i16_builtin_imm(ptr %a, ptr %c) {94; P5600-LABEL: sub_v8i16_builtin_imm:95; P5600: # %bb.0: # %entry96; P5600-NEXT: ld.h $w0, 0($4)97; P5600-NEXT: subvi.h $w0, $w0, 1898; P5600-NEXT: st.h $w0, 0($5)99; P5600-NEXT: jr $ra100; P5600-NEXT: nop101entry:102 %0 = load <8 x i16>, ptr %a, align 16103 %1 = tail call <8 x i16> @llvm.mips.subvi.h(<8 x i16> %0, i32 18)104 store <8 x i16> %1, ptr %c, align 16105 ret void106}107 108declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32 immarg)109define void @sub_v4i32_builtin_imm(ptr %a, ptr %c) {110; P5600-LABEL: sub_v4i32_builtin_imm:111; P5600: # %bb.0: # %entry112; P5600-NEXT: ld.w $w0, 0($4)113; P5600-NEXT: subvi.w $w0, $w0, 25114; P5600-NEXT: st.w $w0, 0($5)115; P5600-NEXT: jr $ra116; P5600-NEXT: nop117entry:118 %0 = load <4 x i32>, ptr %a, align 16119 %1 = tail call <4 x i32> @llvm.mips.subvi.w(<4 x i32> %0, i32 25)120 store <4 x i32> %1, ptr %c, align 16121 ret void122}123 124declare <2 x i64> @llvm.mips.subvi.d(<2 x i64>, i32 immarg)125define void @sub_v2i64_builtin_imm(ptr %a, ptr %c) {126; P5600-LABEL: sub_v2i64_builtin_imm:127; P5600: # %bb.0: # %entry128; P5600-NEXT: ld.d $w0, 0($4)129; P5600-NEXT: subvi.d $w0, $w0, 31130; P5600-NEXT: st.d $w0, 0($5)131; P5600-NEXT: jr $ra132; P5600-NEXT: nop133entry:134 %0 = load <2 x i64>, ptr %a, align 16135 %1 = tail call <2 x i64> @llvm.mips.subvi.d(<2 x i64> %0, i32 31)136 store <2 x i64> %1, ptr %c, align 16137 ret void138}139