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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS323--- |4 5 6 define void @and_i32() {entry: ret void}7 define void @or_i32() {entry: ret void}8 define void @xor_i32() {entry: ret void}9 define void @shl(i32) {entry: ret void}10 define void @ashr(i32) {entry: ret void}11 define void @lshr(i32) {entry: ret void}12 define void @shlv(i32, i32) {entry: ret void}13 define void @ashrv(i32, i32) {entry: ret void}14 define void @lshrv(i32, i32) {entry: ret void}15 16...17---18name: and_i3219alignment: 420legalized: true21tracksRegLiveness: true22body: |23 bb.1.entry:24 liveins: $a0, $a125 26 ; MIPS32-LABEL: name: and_i3227 ; MIPS32: liveins: $a0, $a128 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a029 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a130 ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY1]], [[COPY]]31 ; MIPS32: $v0 = COPY [[AND]](s32)32 ; MIPS32: RetRA implicit $v033 %0:_(s32) = COPY $a034 %1:_(s32) = COPY $a135 %2:_(s32) = G_AND %1, %036 $v0 = COPY %2(s32)37 RetRA implicit $v038 39...40---41name: or_i3242alignment: 443legalized: true44tracksRegLiveness: true45body: |46 bb.1.entry:47 liveins: $a0, $a148 49 ; MIPS32-LABEL: name: or_i3250 ; MIPS32: liveins: $a0, $a151 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a052 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a153 ; MIPS32: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY1]], [[COPY]]54 ; MIPS32: $v0 = COPY [[OR]](s32)55 ; MIPS32: RetRA implicit $v056 %0:_(s32) = COPY $a057 %1:_(s32) = COPY $a158 %2:_(s32) = G_OR %1, %059 $v0 = COPY %2(s32)60 RetRA implicit $v061 62...63---64name: xor_i3265alignment: 466legalized: true67tracksRegLiveness: true68body: |69 bb.1.entry:70 liveins: $a0, $a171 72 ; MIPS32-LABEL: name: xor_i3273 ; MIPS32: liveins: $a0, $a174 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a075 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a176 ; MIPS32: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY1]], [[COPY]]77 ; MIPS32: $v0 = COPY [[XOR]](s32)78 ; MIPS32: RetRA implicit $v079 %0:_(s32) = COPY $a080 %1:_(s32) = COPY $a181 %2:_(s32) = G_XOR %1, %082 $v0 = COPY %2(s32)83 RetRA implicit $v084 85...86---87name: shl88alignment: 489legalized: true90tracksRegLiveness: true91body: |92 bb.1.entry:93 liveins: $a094 95 ; MIPS32-LABEL: name: shl96 ; MIPS32: liveins: $a097 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a098 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 199 ; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[C]]100 ; MIPS32: $v0 = COPY [[SHL]](s32)101 ; MIPS32: RetRA implicit $v0102 %0:_(s32) = COPY $a0103 %1:_(s32) = G_CONSTANT i32 1104 %2:_(s32) = G_SHL %0, %1105 $v0 = COPY %2(s32)106 RetRA implicit $v0107 108...109---110name: ashr111alignment: 4112legalized: true113tracksRegLiveness: true114body: |115 bb.1.entry:116 liveins: $a0117 118 ; MIPS32-LABEL: name: ashr119 ; MIPS32: liveins: $a0120 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0121 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1122 ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[C]]123 ; MIPS32: $v0 = COPY [[ASHR]](s32)124 ; MIPS32: RetRA implicit $v0125 %0:_(s32) = COPY $a0126 %1:_(s32) = G_CONSTANT i32 1127 %2:_(s32) = G_ASHR %0, %1128 $v0 = COPY %2(s32)129 RetRA implicit $v0130 131...132---133name: lshr134alignment: 4135legalized: true136tracksRegLiveness: true137body: |138 bb.1.entry:139 liveins: $a0140 141 ; MIPS32-LABEL: name: lshr142 ; MIPS32: liveins: $a0143 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0144 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1145 ; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[C]]146 ; MIPS32: $v0 = COPY [[LSHR]](s32)147 ; MIPS32: RetRA implicit $v0148 %0:_(s32) = COPY $a0149 %1:_(s32) = G_CONSTANT i32 1150 %2:_(s32) = G_LSHR %0, %1151 $v0 = COPY %2(s32)152 RetRA implicit $v0153 154...155---156name: shlv157alignment: 4158legalized: true159tracksRegLiveness: true160body: |161 bb.1.entry:162 liveins: $a0, $a1163 164 ; MIPS32-LABEL: name: shlv165 ; MIPS32: liveins: $a0, $a1166 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0167 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1168 ; MIPS32: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]]169 ; MIPS32: $v0 = COPY [[SHL]](s32)170 ; MIPS32: RetRA implicit $v0171 %0:_(s32) = COPY $a0172 %1:_(s32) = COPY $a1173 %2:_(s32) = G_SHL %0, %1174 $v0 = COPY %2(s32)175 RetRA implicit $v0176 177...178---179name: ashrv180alignment: 4181legalized: true182tracksRegLiveness: true183body: |184 bb.1.entry:185 liveins: $a0, $a1186 187 ; MIPS32-LABEL: name: ashrv188 ; MIPS32: liveins: $a0, $a1189 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0190 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1191 ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]]192 ; MIPS32: $v0 = COPY [[ASHR]](s32)193 ; MIPS32: RetRA implicit $v0194 %0:_(s32) = COPY $a0195 %1:_(s32) = COPY $a1196 %2:_(s32) = G_ASHR %0, %1197 $v0 = COPY %2(s32)198 RetRA implicit $v0199 200...201---202name: lshrv203alignment: 4204legalized: true205tracksRegLiveness: true206body: |207 bb.1.entry:208 liveins: $a0, $a1209 210 ; MIPS32-LABEL: name: lshrv211 ; MIPS32: liveins: $a0, $a1212 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0213 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1214 ; MIPS32: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]]215 ; MIPS32: $v0 = COPY [[LSHR]](s32)216 ; MIPS32: RetRA implicit $v0217 %0:_(s32) = COPY $a0218 %1:_(s32) = COPY $a1219 %2:_(s32) = G_LSHR %0, %1220 $v0 = COPY %2(s32)221 RetRA implicit $v0222 223...224