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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS323--- |4 5 define i32 @mod4_0_to_11(i32 %a) {6 entry:7 switch i32 %a, label %sw.default [8 i32 0, label %sw.bb9 i32 4, label %sw.bb10 i32 1, label %sw.bb111 i32 5, label %sw.bb112 i32 2, label %sw.bb213 i32 6, label %sw.bb214 i32 3, label %sw.bb315 i32 7, label %sw.bb316 ]17 18 sw.bb: ; preds = %entry, %entry19 ret i32 020 21 sw.bb1: ; preds = %entry, %entry22 ret i32 123 24 sw.bb2: ; preds = %entry, %entry25 ret i32 226 27 sw.bb3: ; preds = %entry, %entry28 ret i32 329 30 sw.default: ; preds = %entry31 br label %sw.epilog32 33 sw.epilog: ; preds = %sw.default34 switch i32 %a, label %sw.default8 [35 i32 8, label %sw.bb436 i32 9, label %sw.bb537 i32 10, label %sw.bb638 i32 11, label %sw.bb739 ]40 41 sw.bb4: ; preds = %sw.epilog42 ret i32 043 44 sw.bb5: ; preds = %sw.epilog45 ret i32 146 47 sw.bb6: ; preds = %sw.epilog48 ret i32 249 50 sw.bb7: ; preds = %sw.epilog51 ret i32 352 53 sw.default8: ; preds = %sw.epilog54 ret i32 -155 }56 57...58---59name: mod4_0_to_1160alignment: 461legalized: true62tracksRegLiveness: true63jumpTable:64 kind: block-address65 entries:66 - id: 067 blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.2', '%bb.3',68 '%bb.4', '%bb.5' ]69 - id: 170 blocks: [ '%bb.8', '%bb.9', '%bb.10', '%bb.11' ]71body: |72 ; MIPS32-LABEL: name: mod4_0_to_1173 ; MIPS32: bb.0.entry:74 ; MIPS32: successors: %bb.6(0x40000000), %bb.1(0x40000000)75 ; MIPS32: liveins: $a076 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a077 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 778 ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 379 ; MIPS32: [[C2:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 280 ; MIPS32: [[C3:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 181 ; MIPS32: [[C4:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 082 ; MIPS32: [[C5:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -183 ; MIPS32: [[C6:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 084 ; MIPS32: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[C6]]85 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[SUB]](s32)86 ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)87 ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY2]]88 ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)89 ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C3]]90 ; MIPS32: G_BRCOND [[AND]](s32), %bb.691 ; MIPS32: bb.1.entry:92 ; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)93 ; MIPS32: [[JUMP_TABLE:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.094 ; MIPS32: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[COPY1]](s32)95 ; MIPS32: bb.2.sw.bb:96 ; MIPS32: $v0 = COPY [[C4]](s32)97 ; MIPS32: RetRA implicit $v098 ; MIPS32: bb.3.sw.bb1:99 ; MIPS32: $v0 = COPY [[C3]](s32)100 ; MIPS32: RetRA implicit $v0101 ; MIPS32: bb.4.sw.bb2:102 ; MIPS32: $v0 = COPY [[C2]](s32)103 ; MIPS32: RetRA implicit $v0104 ; MIPS32: bb.5.sw.bb3:105 ; MIPS32: $v0 = COPY [[C1]](s32)106 ; MIPS32: RetRA implicit $v0107 ; MIPS32: bb.6.sw.default:108 ; MIPS32: successors: %bb.7(0x80000000)109 ; MIPS32: bb.7.sw.epilog:110 ; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000)111 ; MIPS32: [[C7:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 8112 ; MIPS32: [[SUB1:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[C7]]113 ; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[SUB1]](s32)114 ; MIPS32: [[COPY5:%[0-9]+]]:gprb(s32) = COPY [[C1]](s32)115 ; MIPS32: [[ICMP1:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ugt), [[COPY4]](s32), [[COPY5]]116 ; MIPS32: [[C8:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1117 ; MIPS32: [[COPY6:%[0-9]+]]:gprb(s32) = COPY [[ICMP1]](s32)118 ; MIPS32: [[AND1:%[0-9]+]]:gprb(s32) = G_AND [[COPY6]], [[C8]]119 ; MIPS32: G_BRCOND [[AND1]](s32), %bb.13120 ; MIPS32: bb.8.sw.epilog:121 ; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)122 ; MIPS32: [[JUMP_TABLE1:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.1123 ; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY4]](s32)124 ; MIPS32: bb.9.sw.bb4:125 ; MIPS32: $v0 = COPY [[C4]](s32)126 ; MIPS32: RetRA implicit $v0127 ; MIPS32: bb.10.sw.bb5:128 ; MIPS32: $v0 = COPY [[C3]](s32)129 ; MIPS32: RetRA implicit $v0130 ; MIPS32: bb.11.sw.bb6:131 ; MIPS32: $v0 = COPY [[C2]](s32)132 ; MIPS32: RetRA implicit $v0133 ; MIPS32: bb.12.sw.bb7:134 ; MIPS32: $v0 = COPY [[C1]](s32)135 ; MIPS32: RetRA implicit $v0136 ; MIPS32: bb.13.sw.default8:137 ; MIPS32: $v0 = COPY [[C5]](s32)138 ; MIPS32: RetRA implicit $v0139 bb.1.entry:140 liveins: $a0141 142 %0:_(s32) = COPY $a0143 %4:_(s32) = G_CONSTANT i32 7144 %8:_(s32) = G_CONSTANT i32 3145 %9:_(s32) = G_CONSTANT i32 2146 %10:_(s32) = G_CONSTANT i32 1147 %11:_(s32) = G_CONSTANT i32 0148 %18:_(s32) = G_CONSTANT i32 -1149 %1:_(s32) = G_CONSTANT i32 0150 %2:_(s32) = G_SUB %0, %1151 %3:_(s32) = COPY %2(s32)152 %5:_(s32) = COPY %4(s32)153 %22:_(s32) = G_ICMP intpred(ugt), %3(s32), %5154 %23:_(s32) = COPY %22(s32)155 %21:_(s32) = G_AND %23, %10156 G_BRCOND %21(s32), %bb.6157 158 bb.13.entry:159 successors: %bb.2, %bb.3, %bb.4, %bb.5160 161 %7:_(p0) = G_JUMP_TABLE %jump-table.0162 G_BRJT %7(p0), %jump-table.0, %3(s32)163 164 bb.2.sw.bb:165 $v0 = COPY %11(s32)166 RetRA implicit $v0167 168 bb.3.sw.bb1:169 $v0 = COPY %10(s32)170 RetRA implicit $v0171 172 bb.4.sw.bb2:173 $v0 = COPY %9(s32)174 RetRA implicit $v0175 176 bb.5.sw.bb3:177 $v0 = COPY %8(s32)178 RetRA implicit $v0179 180 bb.6.sw.default:181 182 bb.7.sw.epilog:183 %12:_(s32) = G_CONSTANT i32 8184 %13:_(s32) = G_SUB %0, %12185 %14:_(s32) = COPY %13(s32)186 %15:_(s32) = COPY %8(s32)187 %20:_(s32) = G_ICMP intpred(ugt), %14(s32), %15188 %24:_(s32) = G_CONSTANT i32 1189 %25:_(s32) = COPY %20(s32)190 %19:_(s32) = G_AND %25, %24191 G_BRCOND %19(s32), %bb.12192 193 bb.14.sw.epilog:194 successors: %bb.8, %bb.9, %bb.10, %bb.11195 196 %17:_(p0) = G_JUMP_TABLE %jump-table.1197 G_BRJT %17(p0), %jump-table.1, %14(s32)198 199 bb.8.sw.bb4:200 $v0 = COPY %11(s32)201 RetRA implicit $v0202 203 bb.9.sw.bb5:204 $v0 = COPY %10(s32)205 RetRA implicit $v0206 207 bb.10.sw.bb6:208 $v0 = COPY %9(s32)209 RetRA implicit $v0210 211 bb.11.sw.bb7:212 $v0 = COPY %8(s32)213 RetRA implicit $v0214 215 bb.12.sw.default8:216 $v0 = COPY %18(s32)217 RetRA implicit $v0218 219...220