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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS323--- |4 5 define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}6 define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void}7 define void @load4_s32_to_zextLoad4_s64(ptr %px) {entry: ret void}8 define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}9 define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}10 define void @load4_s32_to_sextLoad4_s64(ptr %px) {entry: ret void}11 12...13---14name: load1_s8_to_zextLoad1_s3215alignment: 416legalized: true17tracksRegLiveness: true18body: |19 bb.1.entry:20 liveins: $a021 22 ; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s3223 ; MIPS32: liveins: $a024 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a025 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)26 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)27 ; MIPS32: RetRA implicit $v028 %0:_(p0) = COPY $a029 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)30 $v0 = COPY %2(s32)31 RetRA implicit $v032 33...34---35name: load2_s16_to_zextLoad2_s3236alignment: 437legalized: true38tracksRegLiveness: true39body: |40 bb.1.entry:41 liveins: $a042 43 ; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s3244 ; MIPS32: liveins: $a045 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a046 ; MIPS32: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)47 ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)48 ; MIPS32: RetRA implicit $v049 %0:_(p0) = COPY $a050 %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16) from %ir.px)51 $v0 = COPY %2(s32)52 RetRA implicit $v053 54...55---56name: load4_s32_to_zextLoad4_s6457alignment: 458legalized: true59tracksRegLiveness: true60body: |61 bb.1.entry:62 liveins: $a063 64 ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s6465 ; MIPS32: liveins: $a066 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a067 ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)68 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 069 ; MIPS32: $v0 = COPY [[LOAD]](s32)70 ; MIPS32: $v1 = COPY [[C]](s32)71 ; MIPS32: RetRA implicit $v0, implicit $v172 %0:_(p0) = COPY $a073 %5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)74 %6:_(s32) = G_CONSTANT i32 075 %2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)76 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)77 $v0 = COPY %3(s32)78 $v1 = COPY %4(s32)79 RetRA implicit $v0, implicit $v180 81...82---83name: load1_s8_to_sextLoad1_s3284alignment: 485legalized: true86tracksRegLiveness: true87body: |88 bb.1.entry:89 liveins: $a090 91 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s3292 ; MIPS32: liveins: $a093 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a094 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)95 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)96 ; MIPS32: RetRA implicit $v097 %0:_(p0) = COPY $a098 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)99 $v0 = COPY %2(s32)100 RetRA implicit $v0101 102...103---104name: load2_s16_to_sextLoad2_s32105alignment: 4106legalized: true107tracksRegLiveness: true108body: |109 bb.1.entry:110 liveins: $a0111 112 ; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32113 ; MIPS32: liveins: $a0114 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0115 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)116 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)117 ; MIPS32: RetRA implicit $v0118 %0:_(p0) = COPY $a0119 %2:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16) from %ir.px)120 $v0 = COPY %2(s32)121 RetRA implicit $v0122 123...124---125name: load4_s32_to_sextLoad4_s64126alignment: 4127legalized: true128tracksRegLiveness: true129body: |130 bb.1.entry:131 liveins: $a0132 133 ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64134 ; MIPS32: liveins: $a0135 ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0136 ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.px)137 ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31138 ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0139 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)140 ; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)141 ; MIPS32: $v0 = COPY [[LOAD]](s32)142 ; MIPS32: $v1 = COPY [[ASHR]](s32)143 ; MIPS32: RetRA implicit $v0, implicit $v1144 %0:_(p0) = COPY $a0145 %5:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.px)146 %9:_(s32) = G_CONSTANT i32 31147 %10:_(s32) = G_CONSTANT i32 0148 %8:_(s32) = COPY %9(s32)149 %7:_(s32) = G_ASHR %5, %8(s32)150 %2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)151 %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)152 $v0 = COPY %3(s32)153 $v1 = COPY %4(s32)154 RetRA implicit $v0, implicit $v1155 156...157 158