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1; RUN: llc -mtriple=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS2; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+xgot < %s \3; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MIPS-XGOT4 5; RUN: llc -mtriple=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM6; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+xgot,+micromips < %s \7; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MM-XGOT8 9; REQUIRES: asserts10 11; Tests that the correct ISA is selected for computing a global address.12 13@x = global i32 014@a = global i32 115declare i32 @y(ptr, i32)16 17define i32 @z() {18entry:19 %0 = load i32, ptr @a, align 420 %1 = call i32 @y(ptr @x, i32 %0)21 ret i32 %122}23 24; MIPS-LABEL: ===== Instruction selection ends:25; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<ptr @x> 0 [TF=4]26; MIPS: t{{.*}}: i32 = ADDiu t[[A]], TargetGlobalAddress:i32<ptr @x> 0 [TF=5]27 28; MIPS-XGOT-LABEL: ===== Instruction selection ends:29; MIPS-XGOT: t[[B:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<ptr @x> 0 [TF=20]30; MIPS-XGOT: t[[C:[0-9]+]]: i32 = ADDu t[[B]], Register:i32 %031; MIPS-XGOT: t{{.*}}: i32,ch = LW<Mem:(load (s32) from got)> t[[C]], TargetGlobalAddress:i32<ptr @x> 0 [TF=21], t{{.*}}32 33; MM-LABEL: ===== Instruction selection ends:34; MM: t[[A:[0-9]+]]: i32 = LUi_MM TargetGlobalAddress:i32<ptr @x> 0 [TF=4]35; MM: t{{.*}}: i32 = ADDiu_MM t[[A]], TargetGlobalAddress:i32<ptr @x> 0 [TF=5]36 37; MM-XGOT-LABEL: ===== Instruction selection ends:38; MM-XGOT: t[[B:[0-9]+]]: i32 = LUi_MM TargetGlobalAddress:i32<ptr @x> 0 [TF=20]39; MM-XGOT: t[[C:[0-9]+]]: i32 = ADDU16_MM t[[B]], Register:i32 %040; MM-XGOT: t{{.*}}: i32,ch = LW_MM<Mem:(load (s32) from got)> t[[C]], TargetGlobalAddress:i32<ptr @x> 0 [TF=21], t041