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1; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | \2; RUN: FileCheck %s -check-prefixes=ALL,PRE-R63; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | \4; RUN: FileCheck %s -check-prefixes=ALL,PRE-R65; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | \6; RUN: FileCheck %s -check-prefixes=ALL,PRE-R67; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | \8; RUN: FileCheck %s -check-prefixes=ALL,PRE-R69; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | \10; RUN: FileCheck %s -check-prefixes=ALL,PRE-R611; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | \12; RUN: FileCheck %s -check-prefixes=ALL,PRE-R613; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | \14; RUN: FileCheck %s -check-prefixes=ALL,R615 16; Check that we don't emit redundant SLLs for sequences of17; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)18define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {19entry:20; ALL-LABEL: udiv_i8:21 22 ; PRE-R6-NOT: sll {{.*}}23 ; PRE-R6: divu $zero, $4, $524 ; PRE-R6: teq $5, $zero, 725 ; PRE-R6: mflo $226 27 ; R6-NOT: sll {{.*}}28 ; R6: divu $2, $4, $529 ; R6: teq $5, $zero, 730 31 %r = udiv i8 %a, %b32 ret i8 %r33}34 35; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32))36define i64 @foo1(i64 zeroext %var) {37entry:38; ALL-LABEL: foo1:39 40 %shr = lshr i64 %var, 3241 %cmp = icmp eq i64 %shr, 042 br i1 %cmp, label %if.end6, label %if.then43 44 ; ALL: dsrl $[[T0:[0-9]+]], $4, 3245 ; ALL: sll $[[T1:[0-9]+]], $[[T0]], 046 if.then: ; preds = %entry47 %conv = trunc i64 %shr to i3248 %cmp2 = icmp slt i32 %conv, 049 br i1 %cmp2, label %if.then4, label %if.else50 51 if.then4: ; preds = %if.then52 %add = add i64 %var, 1653 br label %if.end654 55 if.else: ; preds = %if.then56 %add5 = add i64 %var, 3257 br label %if.end658 59 if.end6: ; preds = %entry, %if.then4, %if.else60 %var.addr.0 = phi i64 [ %add, %if.then4 ], [ %add5, %if.else ], [ %var, %entry ]61 ret i64 %var.addr.062}63