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1; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \2; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC %s3; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \4; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC %s5; RUN: llc -mtriple=mips64 -debug-only=isel -mips-tail-calls=1 \6; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC64 %s7; RUN: llc -mtriple=mips64 -debug-only=isel -mips-tail-calls=1 \8; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC64 %s9; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \10; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s11; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \12; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s13; RUN: llc -mtriple=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \14; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s15; RUN: llc -mtriple=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \16; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s17; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \18; RUN: -relocation-model=pic -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s19; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \20; RUN: -relocation-model=static -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s21 22; REQUIRES: asserts23 24; Test that the correct pseudo instructions are generated for indirect25; branches and tail calls. Previously, the order of the DAG matcher table26; determined if the correct instruction was selected for mips16.27 28declare protected void @a()29 30define void @test1(i32 %a) {31entry:32 %0 = trunc i32 %a to i133 %1 = select i1 %0,34 ptr blockaddress(@test1, %bb),35 ptr blockaddress(@test1, %bb6)36 indirectbr ptr %1, [label %bb, label %bb6]37 38; STATIC: PseudoIndirectBranch39; STATIC-MM: PseudoIndirectBranch40; STATIC-NOT: PseudoIndirectBranch6441; STATIC64: PseudoIndirectBranch6442; PIC: PseudoIndirectBranch43; PIC-NOT: PseudoIndirectBranch6444; PIC64: PseudoIndirectBranch6445; MIPS16: JrcRx1646bb:47 ret void48 49bb6:50 tail call void @a()51 52; STATIC: TAILCALL53; STATIC-NOT: TAILCALL_MM54; STATIC-MM: TAILCALL_MM55; PIC: TAILCALLREG56; PIC-NOT: TAILCALLREG6457; PIC64: TAILCALLREG6458; MIPS16: RetRA1659 ret void60}61