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1; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 \2; RUN: | FileCheck %s -check-prefix=MIPS323; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \4; RUN: | FileCheck %s -check-prefix=MM5; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 \6; RUN: | FileCheck %s -check-prefix=MIPS647; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+mips16 \8; RUN: | FileCheck %s -check-prefix=MIPS169 10define i32 @bswap32(i32 signext %x) nounwind readnone {11entry:12; MIPS32-LABEL: bswap32:13; MIPS32: wsbh $[[R0:[0-9]+]]14; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 1615 16; MM-LABEL: bswap32:17; MM: wsbh $[[R0:[0-9]+]]18; MM: rotr ${{[0-9]+}}, $[[R0]], 1619 20; MIPS64-LABEL: bswap32:21; MIPS64: wsbh $[[R0:[0-9]+]]22; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 1623 24; MIPS16-LABEL: bswap32:25; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 826; MIPS16-DAG: li $[[R4:[0-9]+]], 6528027; MIPS16-DAG: and $[[R0]], $[[R4]]28; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 2429; MIPS16-DAG: or $[[R1]], $[[R0]]30; MIPS16-DAG: and $[[R4]], $431; MIPS16-DAG: sll $[[R2:[0-9]+]], $[[R4]], 832; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 2433; MIPS16-DAG: or $[[R3]], $[[R2]]34; MIPS16-DAG: or $[[R3]], $[[R1]]35 36 %or.3 = call i32 @llvm.bswap.i32(i32 %x)37 ret i32 %or.338}39 40define i64 @bswap64(i64 signext %x) nounwind readnone {41entry:42; MIPS32-LABEL: bswap64:43; MIPS32: wsbh $[[R0:[0-9]+]]44; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 1645; MIPS32: wsbh $[[R0:[0-9]+]]46; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 1647 48; MM-LABEL: bswap64:49; MM: wsbh $[[R0:[0-9]+]]50; MM: rotr ${{[0-9]+}}, $[[R0]], 1651; MM: wsbh $[[R0:[0-9]+]]52; MM: rotr ${{[0-9]+}}, $[[R0]], 1653 54; MIPS64-LABEL: bswap64:55; MIPS64: dsbh $[[R0:[0-9]+]]56; MIPS64: dshd ${{[0-9]+}}, $[[R0]]57 58; MIPS16-LABEL: bswap64:59; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 860; MIPS16-DAG: li $[[R4:[0-9]+]], 6528061; MIPS16-DAG: and $[[R0]], $[[R4]]62; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 2463; MIPS16-DAG: or $[[R1]], $[[R0]]64; MIPS16-DAG: sll $[[R3:[0-9]+]], $5, 2465; MIPS16-DAG: and $5, $[[R4]]66; MIPS16-DAG: sll $[[R2:[0-9]+]], $5, 867; MIPS16-DAG: or $[[R0]], $[[R3]]68; MIPS16-DAG: or $[[R0]], $[[R1]]69; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 870; MIPS16-DAG: and $[[R0]], $[[R4]]71; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 2472; MIPS16-DAG: or $[[R1]], $[[R0]]73; MIPS16-DAG: and $[[R4]], $474; MIPS16-DAG: sll $[[R2:[0-9]+]], $[[R4]], 875; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 2476; MIPS16-DAG: or $[[R3]], $[[R2]]77; MIPS16-DAG: or $[[R3]], $[[R1]]78 79 %or.7 = call i64 @llvm.bswap.i64(i64 %x)80 ret i64 %or.781}82 83define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone {84entry:85; MIPS32-LABEL: bswapv4i32:86; MIPS32-DAG: wsbh $[[R0:[0-9]+]]87; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 1688; MIPS32-DAG: wsbh $[[R0:[0-9]+]]89; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 1690; MIPS32-DAG: wsbh $[[R0:[0-9]+]]91; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 1692; MIPS32-DAG: wsbh $[[R0:[0-9]+]]93; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 1694 95; MM-LABEL: bswapv4i32:96; MM-DAG: wsbh $[[R0:[0-9]+]]97; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 1698; MM-DAG: wsbh $[[R0:[0-9]+]]99; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16100; MM-DAG: wsbh $[[R0:[0-9]+]]101; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16102; MM-DAG: wsbh $[[R0:[0-9]+]]103; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16104 105; MIPS64-LABEL: bswapv4i32:106; MIPS64-DAG: wsbh $[[R0:[0-9]+]]107; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16108; MIPS64-DAG: wsbh $[[R0:[0-9]+]]109; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16110; MIPS64-DAG: wsbh $[[R0:[0-9]+]]111; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16112; MIPS64-DAG: wsbh $[[R0:[0-9]+]]113; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16114 115; Don't bother with a MIPS16 version. It's just bswap32 repeated four times and116; would be very long117 118 %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x)119 ret <4 x i32> %ret120}121 122declare i32 @llvm.bswap.i32(i32) nounwind readnone123 124declare i64 @llvm.bswap.i64(i64) nounwind readnone125 126declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone127