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1; RUN: llc -mtriple=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s2; RUN: llc -mtriple=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s3 4; RUN-TODO: llc -mtriple=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s5; RUN-TODO: llc -mtriple=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s6 7; RUN: llc -mtriple=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s8; RUN: llc -mtriple=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s9 10; RUN: llc -mtriple=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s11; RUN: llc -mtriple=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s12 13; Test the integer arguments for all ABI's and byte orders as specified by14; section 5 of MD00305 (MIPS ABIs Described).15;16; N32/N64 are identical in this area so their checks have been combined into17; the 'NEW' prefix (the N stands for New).18;19; Varargs are covered in arguments-hard-float-varargs.ll.20 21@bytes = global [11 x i8] zeroinitializer22@dwords = global [11 x i64] zeroinitializer23@floats = global [11 x float] zeroinitializer24@doubles = global [11 x double] zeroinitializer25 26define void @align_to_arg_slots(i8 signext %a, i8 signext %b, i8 signext %c,27 i8 signext %d, i8 signext %e, i8 signext %f,28 i8 signext %g, i8 signext %h, i8 signext %i,29 i8 signext %j) nounwind {30entry:31 %0 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 132 store volatile i8 %a, ptr %033 %1 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 234 store volatile i8 %b, ptr %135 %2 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 336 store volatile i8 %c, ptr %237 %3 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 438 store volatile i8 %d, ptr %339 %4 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 540 store volatile i8 %e, ptr %441 %5 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 642 store volatile i8 %f, ptr %543 %6 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 744 store volatile i8 %g, ptr %645 %7 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 846 store volatile i8 %h, ptr %747 %8 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 948 store volatile i8 %i, ptr %849 %9 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 1050 store volatile i8 %j, ptr %951 ret void52}53 54; ALL-LABEL: align_to_arg_slots:55; We won't test the way the global address is calculated in this test. This is56; just to get the register number for the other checks.57; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)58; SYM64-DAG: daddiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)59 60; The first four arguments are the same in O32/N32/N6461; ALL-DAG: sb $4, 1([[R1]])62; ALL-DAG: sb $5, 2([[R1]])63; ALL-DAG: sb $6, 3([[R1]])64; ALL-DAG: sb $7, 4([[R1]])65 66; N32/N64 get an extra four arguments in registers67; O32 starts loading from the stack. The addresses start at 16 because space is68; always reserved for the first four arguments.69; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)70; O32-DAG: sb [[R3]], 5([[R1]])71; NEW-DAG: sb $8, 5([[R1]])72; O32-DAG: lw [[R3:\$[0-9]+]], 20($sp)73; O32-DAG: sb [[R3]], 6([[R1]])74; NEW-DAG: sb $9, 6([[R1]])75; O32-DAG: lw [[R3:\$[0-9]+]], 24($sp)76; O32-DAG: sb [[R3]], 7([[R1]])77; NEW-DAG: sb $10, 7([[R1]])78; O32-DAG: lw [[R3:\$[0-9]+]], 28($sp)79; O32-DAG: sb [[R3]], 8([[R1]])80; NEW-DAG: sb $11, 8([[R1]])81 82; O32/N32/N64 are accessing the stack at this point.83; Unlike O32, N32/N64 do not reserve space for the arguments.84; increase by 4 for O32 and 8 for N32/N64.85; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)86; O32-DAG: sb [[R3]], 9([[R1]])87; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)88; NEW-DAG: sb [[R3]], 9([[R1]])89; O32-DAG: lw [[R3:\$[0-9]+]], 36($sp)90; O32-DAG: sb [[R3]], 10([[R1]])91; NEW-DAG: ld [[R3:\$[0-9]+]], 8($sp)92; NEW-DAG: sb [[R3]], 10([[R1]])93 94define void @slot_skipping(i8 signext %a, i64 signext %b, i8 signext %c,95 i8 signext %d, i8 signext %e, i8 signext %f,96 i8 signext %g, i64 signext %i, i8 signext %j) nounwind {97entry:98 %0 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 199 store volatile i8 %a, ptr %0100 %1 = getelementptr [11 x i64], ptr @dwords, i32 0, i32 1101 store volatile i64 %b, ptr %1102 %2 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 2103 store volatile i8 %c, ptr %2104 %3 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 3105 store volatile i8 %d, ptr %3106 %4 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 4107 store volatile i8 %e, ptr %4108 %5 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 5109 store volatile i8 %f, ptr %5110 %6 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 6111 store volatile i8 %g, ptr %6112 %7 = getelementptr [11 x i64], ptr @dwords, i32 0, i32 2113 store volatile i64 %i, ptr %7114 %8 = getelementptr [11 x i8], ptr @bytes, i32 0, i32 7115 store volatile i8 %j, ptr %8116 ret void117}118 119; ALL-LABEL: slot_skipping:120; We won't test the way the global address is calculated in this test. This is121; just to get the register number for the other checks.122; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)123; SYM64-DAG: daddiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)124; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)125; SYM64-DAG: daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)126 127; The first argument is the same in O32/N32/N64.128; ALL-DAG: sb $4, 1([[R1]])129 130; The second slot is insufficiently aligned for i64 on O32 so it is skipped.131; Also, i64 occupies two slots on O32 and only one for N32/N64.132; O32-DAG: sw $6, 8([[R2]])133; O32-DAG: sw $7, 12([[R2]])134; NEW-DAG: sd $5, 8([[R2]])135 136; N32/N64 get an extra four arguments in registers and still have two left from137; the first four.138; O32 starts loading from the stack. The addresses start at 16 because space is139; always reserved for the first four arguments.140; It's not clear why O32 uses lbu for this argument, but it's not wrong so we'll141; accept it for now. The only IR difference is that this argument has142; anyext from i8 and align 8 on it.143; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)144; O32-DAG: sb [[R3]], 2([[R1]])145; NEW-DAG: sb $6, 2([[R1]])146; O32-DAG: lw [[R3:\$[0-9]+]], 20($sp)147; O32-DAG: sb [[R3]], 3([[R1]])148; NEW-DAG: sb $7, 3([[R1]])149; O32-DAG: lw [[R3:\$[0-9]+]], 24($sp)150; O32-DAG: sb [[R3]], 4([[R1]])151; NEW-DAG: sb $8, 4([[R1]])152; O32-DAG: lw [[R3:\$[0-9]+]], 28($sp)153; O32-DAG: sb [[R3]], 5([[R1]])154; NEW-DAG: sb $9, 5([[R1]])155 156; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)157; O32-DAG: sb [[R3]], 6([[R1]])158; NEW-DAG: sb $10, 6([[R1]])159 160; O32-DAG: lw [[R3:\$[0-9]+]], 40($sp)161; O32-DAG: sw [[R3]], 16([[R2]])162; O32-DAG: lw [[R3:\$[0-9]+]], 44($sp)163; O32-DAG: sw [[R3]], 20([[R2]])164; NEW-DAG: sd $11, 16([[R2]])165 166; O32/N32/N64 are accessing the stack at this point.167; Unlike O32, N32/N64 do not reserve space for the arguments.168; increase by 4 for O32 and 8 for N32/N64.169; O32-DAG: lw [[R3:\$[0-9]+]], 48($sp)170; O32-DAG: sb [[R3]], 7([[R1]])171; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)172; NEW-DAG: sb [[R3]], 7([[R1]])173