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1; RUN: llc -mtriple=mips -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,O32 %s2; RUN: llc -mtriple=mipsel -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,O32 %s3 4; RUN: llc -mtriple=mips64 -target-abi n32 -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,N32 %s5; RUN: llc -mtriple=mips64el -target-abi n32 -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,N32 %s6; RUN: llc -mtriple=mips64 -target-abi n32 -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s7; RUN: llc -mtriple=mips64el -target-abi n32 -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s8 9; RUN: llc -mtriple=mips64 -target-abi n64 -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,N64 %s10; RUN: llc -mtriple=mips64el -target-abi n64 -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,N64 %s11; RUN: llc -mtriple=mips64 -target-abi n64 -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s12; RUN: llc -mtriple=mips64el -target-abi n64 -mattr=+single-float < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s13 14define void @fpu_clobber() nounwind {15entry:16 call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()17 ret void18}19 20; ALL-LABEL: fpu_clobber:21; ALL-INV-NOT: swc1 $f0,22; ALL-INV-NOT: swc1 $f1,23; ALL-INV-NOT: swc1 $f2,24; ALL-INV-NOT: swc1 $f3,25; ALL-INV-NOT: swc1 $f4,26; ALL-INV-NOT: swc1 $f5,27; ALL-INV-NOT: swc1 $f6,28; ALL-INV-NOT: swc1 $f7,29; ALL-INV-NOT: swc1 $f8,30; ALL-INV-NOT: swc1 $f9,31; ALL-INV-NOT: swc1 $f10,32; ALL-INV-NOT: swc1 $f11,33; ALL-INV-NOT: swc1 $f12,34; ALL-INV-NOT: swc1 $f13,35; ALL-INV-NOT: swc1 $f14,36; ALL-INV-NOT: swc1 $f15,37; ALL-INV-NOT: swc1 $f16,38; ALL-INV-NOT: swc1 $f17,39; ALL-INV-NOT: swc1 $f18,40; ALL-INV-NOT: swc1 $f19,41 42; O32: addiu $sp, $sp, -4843; O32-DAG: swc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)44; O32-DAG: swc1 [[F21:\$f21]], [[OFF21:[0-9]+]]($sp)45; O32-DAG: swc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp)46; O32-DAG: swc1 [[F23:\$f23]], [[OFF23:[0-9]+]]($sp)47; O32-DAG: swc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)48; O32-DAG: swc1 [[F25:\$f25]], [[OFF25:[0-9]+]]($sp)49; O32-DAG: swc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)50; O32-DAG: swc1 [[F27:\$f27]], [[OFF27:[0-9]+]]($sp)51; O32-DAG: swc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)52; O32-DAG: swc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)53; O32-DAG: swc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)54; O32-DAG: swc1 [[F31:\$f31]], [[OFF31:[0-9]+]]($sp)55; O32-DAG: lwc1 [[F20]], [[OFF20]]($sp)56; O32-DAG: lwc1 [[F21]], [[OFF21]]($sp)57; O32-DAG: lwc1 [[F22]], [[OFF22]]($sp)58; O32-DAG: lwc1 [[F23]], [[OFF23]]($sp)59; O32-DAG: lwc1 [[F24]], [[OFF24]]($sp)60; O32-DAG: lwc1 [[F25]], [[OFF25]]($sp)61; O32-DAG: lwc1 [[F26]], [[OFF26]]($sp)62; O32-DAG: lwc1 [[F27]], [[OFF27]]($sp)63; O32-DAG: lwc1 [[F28]], [[OFF28]]($sp)64; O32-DAG: lwc1 [[F29]], [[OFF29]]($sp)65; O32-DAG: lwc1 [[F30]], [[OFF30]]($sp)66; O32-DAG: lwc1 [[F31]], [[OFF31]]($sp)67; O32: addiu $sp, $sp, 4868 69; N32: addiu $sp, $sp, -3270; N32-DAG: swc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)71; N32-INV-NOT: swc1 $f21,72; N32-DAG: swc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp)73; N32-INV-NOT: swc1 $f23,74; N32-DAG: swc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)75; N32-INV-NOT: swc1 $f25,76; N32-DAG: swc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)77; N32-INV-NOT: swc1 $f27,78; N32-DAG: swc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)79; N32-INV-NOT: swc1 $f29,80; N32-DAG: swc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)81; N32-INV-NOT: swc1 $f31,82; N32-DAG: lwc1 [[F20]], [[OFF20]]($sp)83; N32-DAG: lwc1 [[F22]], [[OFF22]]($sp)84; N32-DAG: lwc1 [[F24]], [[OFF24]]($sp)85; N32-DAG: lwc1 [[F26]], [[OFF26]]($sp)86; N32-DAG: lwc1 [[F28]], [[OFF28]]($sp)87; N32-DAG: lwc1 [[F30]], [[OFF30]]($sp)88; N32: addiu $sp, $sp, 3289 90; N64: addiu $sp, $sp, -3291; N64-INV-NOT: swc1 $f20,92; N64-INV-NOT: swc1 $f21,93; N64-INV-NOT: swc1 $f22,94; N64-INV-NOT: swc1 $f23,95; N64-DAG: swc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)96; N64-DAG: swc1 [[F25:\$f25]], [[OFF25:[0-9]+]]($sp)97; N64-DAG: swc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)98; N64-DAG: swc1 [[F27:\$f27]], [[OFF27:[0-9]+]]($sp)99; N64-DAG: swc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)100; N64-DAG: swc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)101; N64-DAG: swc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)102; N64-DAG: swc1 [[F31:\$f31]], [[OFF31:[0-9]+]]($sp)103; N64-DAG: lwc1 [[F24]], [[OFF24]]($sp)104; N64-DAG: lwc1 [[F25]], [[OFF25]]($sp)105; N64-DAG: lwc1 [[F26]], [[OFF26]]($sp)106; N64-DAG: lwc1 [[F27]], [[OFF27]]($sp)107; N64-DAG: lwc1 [[F28]], [[OFF28]]($sp)108; N64-DAG: lwc1 [[F29]], [[OFF29]]($sp)109; N64-DAG: lwc1 [[F30]], [[OFF30]]($sp)110; N64-DAG: lwc1 [[F31]], [[OFF31]]($sp)111; N64: addiu $sp, $sp, 32