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1; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV2; RUN: llc -mtriple=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV3; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV4; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMP5; RUN: llc -mtriple=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV6; RUN: llc -mtriple=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV7; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMP8 9@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 410@i3 = common global ptr null, align 411 12; ALL-LABEL: cmov1:13 14; 32-CMOV-DAG: lw $[[R0:[0-9]+]], %got(i3)15; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)16; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $417; 32-CMOV-DAG: lw $2, 0($[[R0]])18 19; 32-CMP-DAG: lw $[[R0:[0-9]+]], %got(i3)20; 32-CMP-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)21; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[R1]], $422; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[R0]], $423; 32-CMP-DAG: or $[[T2:[0-9]+]], $[[T0]], $[[T1]]24; 32-CMP-DAG: lw $2, 0($[[T2]])25 26; 64-CMOV-DAG: ldr $[[R0:[0-9]+]]27; 64-CMOV-DAG: ld $[[R1:[0-9]+]], %got_disp(i1)28; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $429 30; 64-CMP-DAG: ld $[[R0:[0-9]+]], %got_disp(i3)(31; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(i1)32; FIXME: This sll works around an implementation detail in the code generator33; (setcc's result is i32 so bits 32-63 are undefined). It's not really34; needed.35; 64-CMP-DAG: sll $[[CC:[0-9]+]], $4, 036; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[R1]], $[[CC]]37; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[R0]], $[[CC]]38; 64-CMP-DAG: or $[[T2:[0-9]+]], $[[T0]], $[[T1]]39; 64-CMP-DAG: ld $2, 0($[[T2]])40 41define ptr @cmov1(i32 signext %s) nounwind readonly {42entry:43 %tobool = icmp ne i32 %s, 044 %tmp1 = load ptr, ptr @i3, align 445 %cond = select i1 %tobool, ptr @i1, ptr %tmp146 ret ptr %cond47}48 49@c = global i32 1, align 450@d = global i32 0, align 451 52; ALL-LABEL: cmov2:53 54; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d)55; 32-CMOV-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c)56; 32-CMOV-DAG: movn $[[R1]], $[[R0]], $457; 32-CMOV-DAG: lw $2, 0($[[R0]])58 59; 32-CMP-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d)60; 32-CMP-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c)61; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[R0]], $462; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[R1]], $463; 32-CMP-DAG: or $[[T2:[0-9]+]], $[[T0]], $[[T1]]64; 32-CMP-DAG: lw $2, 0($[[T2]])65 66; 64-CMOV: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)67; 64-CMOV: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)68; 64-CMOV: movn $[[R1]], $[[R0]], $469 70; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)71; 64-CMP-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)72; FIXME: This sll works around an implementation detail in the code generator73; (setcc's result is i32 so bits 32-63 are undefined). It's not really74; needed.75; 64-CMP-DAG: sll $[[CC:[0-9]+]], $4, 076; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[R0]], $[[CC]]77; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[R1]], $[[CC]]78; 64-CMP-DAG: or $[[T2:[0-9]+]], $[[T0]], $[[T1]]79; 64-CMP-DAG: lw $2, 0($[[T2]])80 81define i32 @cmov2(i32 signext %s) nounwind readonly {82entry:83 %tobool = icmp ne i32 %s, 084 %tmp1 = load i32, ptr @c, align 485 %tmp2 = load i32, ptr @d, align 486 %cond = select i1 %tobool, i32 %tmp1, i32 %tmp287 ret i32 %cond88}89 90; ALL-LABEL: cmov3:91 92; We won't check the result register since we can't know if the move is first93; or last. We do know it will be either one of two registers so we can at least94; check that.95 96; 32-CMOV: xori $[[R0:[0-9]+]], $4, 23497; 32-CMOV: movz ${{[26]}}, $5, $[[R0]]98 99; 32-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234100; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $5, $[[CC]]101; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $6, $[[CC]]102; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]103 104; 64-CMOV: xori $[[R0:[0-9]+]], $4, 234105; 64-CMOV: movz ${{[26]}}, $5, $[[R0]]106 107; 64-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234108; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $5, $[[CC]]109; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $6, $[[CC]]110; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]111 112define i32 @cmov3(i32 signext %a, i32 signext %b, i32 signext %c) nounwind readnone {113entry:114 %cmp = icmp eq i32 %a, 234115 %cond = select i1 %cmp, i32 %b, i32 %c116 ret i32 %cond117}118 119; ALL-LABEL: cmov3_ne:120 121; We won't check the result register since we can't know if the move is first122; or last. We do know it will be either one of two registers so we can at least123; check that.124 125; FIXME: Use xori instead of addiu+xor.126; 32-CMOV: addiu $[[R0:[0-9]+]], $zero, 234127; 32-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]128; 32-CMOV: movn ${{[26]}}, $5, $[[R1]]129 130; 32-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234131; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]]132; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[CC]]133; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]134 135; FIXME: Use xori instead of addiu+xor.136; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234137; 64-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]138; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]139 140; 64-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234141; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]]142; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[CC]]143; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]144 145define i32 @cmov3_ne(i32 signext %a, i32 signext %b, i32 signext %c) nounwind readnone {146entry:147 %cmp = icmp ne i32 %a, 234148 %cond = select i1 %cmp, i32 %b, i32 %c149 ret i32 %cond150}151 152; ALL-LABEL: cmov4:153 154; We won't check the result register since we can't know if the move is first155; or last. We do know it will be one of two registers so we can at least check156; that.157 158; 32-CMOV-DAG: xori $[[R0:[0-9]+]], $4, 234159; 32-CMOV-DAG: lw $[[R1:2]], 16($sp)160; 32-CMOV-DAG: lw $[[R2:3]], 20($sp)161; 32-CMOV-DAG: movz $[[R1]], $6, $[[R0]]162; 32-CMOV-DAG: movz $[[R2]], $7, $[[R0]]163 164; 32-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234165; 32-CMP-DAG: lw $[[R1:[0-9]+]], 16($sp)166; 32-CMP-DAG: lw $[[R2:[0-9]+]], 20($sp)167; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $6, $[[R0]]168; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $7, $[[R0]]169; 32-CMP-DAG: selnez $[[T2:[0-9]+]], $[[R1]], $[[R0]]170; 32-CMP-DAG: selnez $[[T3:[0-9]+]], $[[R2]], $[[R0]]171; 32-CMP-DAG: or $2, $[[T0]], $[[T2]]172; 32-CMP-DAG: or $3, $[[T1]], $[[T3]]173 174; 64-CMOV: xori $[[R0:[0-9]+]], $4, 234175; 64-CMOV: movz ${{[26]}}, $5, $[[R0]]176 177; 64-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234178; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $5, $[[R0]]179; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $6, $[[R0]]180; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]181 182define i64 @cmov4(i32 signext %a, i64 %b, i64 %c) nounwind readnone {183entry:184 %cmp = icmp eq i32 %a, 234185 %cond = select i1 %cmp, i64 %b, i64 %c186 ret i64 %cond187}188 189; ALL-LABEL: cmov4_ne:190 191; We won't check the result register since we can't know if the move is first192; or last. We do know it will be one of two registers so we can at least check193; that.194 195; FIXME: Use xori instead of addiu+xor.196; 32-CMOV-DAG: addiu $[[R0:[0-9]+]], $zero, 234197; 32-CMOV-DAG: xor $[[R1:[0-9]+]], $4, $[[R0]]198; 32-CMOV-DAG: lw $[[R2:2]], 16($sp)199; 32-CMOV-DAG: lw $[[R3:3]], 20($sp)200; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]]201; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]]202 203; 32-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234204; 32-CMP-DAG: lw $[[R1:[0-9]+]], 16($sp)205; 32-CMP-DAG: lw $[[R2:[0-9]+]], 20($sp)206; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $6, $[[R0]]207; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $7, $[[R0]]208; 32-CMP-DAG: seleqz $[[T2:[0-9]+]], $[[R1]], $[[R0]]209; 32-CMP-DAG: seleqz $[[T3:[0-9]+]], $[[R2]], $[[R0]]210; 32-CMP-DAG: or $2, $[[T0]], $[[T2]]211; 32-CMP-DAG: or $3, $[[T1]], $[[T3]]212 213; FIXME: Use xori instead of addiu+xor.214; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234215; 64-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]]216; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]217 218; 64-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234219; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[R0]]220; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $6, $[[R0]]221; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]222 223define i64 @cmov4_ne(i32 signext %a, i64 %b, i64 %c) nounwind readnone {224entry:225 %cmp = icmp ne i32 %a, 234226 %cond = select i1 %cmp, i64 %b, i64 %c227 ret i64 %cond228}229 230; slti and conditional move.231;232; Check that, pattern233; (select (setgt a, N), t, f)234; turns into235; (movz t, (setlt a, N + 1), f)236; if N + 1 fits in 16-bit.237 238; ALL-LABEL: slti0:239 240; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3241; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5242; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767243; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]244 245; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3246; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5247; 32-CMP-DAG: slti $[[R0:[0-9]+]], $4, 32767248; FIXME: We can do better than this by using selccz to choose between +0 and +2249; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]250; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]251; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]252 253; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3254; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5255; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767256; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]257 258; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3259; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5260; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, 32767261; FIXME: We can do better than this by using selccz to choose between +0 and +2262; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]263; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]264; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]265 266define i32 @slti0(i32 signext %a) {267entry:268 %cmp = icmp sgt i32 %a, 32766269 %cond = select i1 %cmp, i32 3, i32 5270 ret i32 %cond271}272 273; ALL-LABEL: slti1:274 275; 32-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7276; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5277; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], $zero, 32767278; 32-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4279; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]280 281; 32-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7282; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5283; 32-CMP-DAG: addiu $[[I32767:[0-9]+]], $zero, 32767284; 32-CMP-DAG: slt $[[R0:[0-9]+]], $[[I32767]], $4285; FIXME: We can do better than this by using selccz to choose between -0 and -2286; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I7]], $[[R0]]287; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]288; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]289 290; 64-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7291; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5292; 64-CMOV-DAG: addiu $[[R1:[0-9]+]], $zero, 32767293; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4294; 64-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]295 296; 64-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7297; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5298; 64-CMP-DAG: addiu $[[R1:[0-9]+]], $zero, 32767299; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4300; FIXME: We can do better than this by using selccz to choose between -0 and -2301; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I7]], $[[R0]]302; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]303; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]304 305define i32 @slti1(i32 signext %a) {306entry:307 %cmp = icmp sgt i32 %a, 32767308 %cond = select i1 %cmp, i32 7, i32 5309 ret i32 %cond310}311 312; ALL-LABEL: slti2:313 314; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3315; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5316; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768317; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]318 319; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3320; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5321; 32-CMP-DAG: slti $[[R0:[0-9]+]], $4, -32768322; FIXME: We can do better than this by using selccz to choose between +0 and +2323; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]324; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]325; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]326 327; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3328; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5329; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768330; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]331 332; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3333; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5334; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, -32768335; FIXME: We can do better than this by using selccz to choose between +0 and +2336; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]337; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]338; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]339 340define i32 @slti2(i32 signext %a) {341entry:342 %cmp = icmp sgt i32 %a, -32769343 %cond = select i1 %cmp, i32 3, i32 5344 ret i32 %cond345}346 347; ALL-LABEL: slti3:348 349; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3350; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5351; 32-CMOV-DAG: lui $[[R1:[0-9]+]], 65535352; 32-CMOV-DAG: ori $[[R1]], $[[R1]], 32766353; 32-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4354; 32-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]]355 356; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3357; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5358; 32-CMP-DAG: lui $[[IMM:[0-9]+]], 65535359; 32-CMP-DAG: ori $[[IMM]], $[[IMM]], 32766360; 32-CMP-DAG: slt $[[R0:[0-9]+]], $[[I32767]], $4361; FIXME: We can do better than this by using selccz to choose between -0 and -2362; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]363; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]364; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]365 366; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3367; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5368; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535369; 64-CMOV-DAG: ori $[[R1]], $[[R1]], 32766370; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4371; 64-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]]372 373; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3374; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5375; 64-CMP-DAG: lui $[[IMM:[0-9]+]], 65535376; 64-CMP-DAG: ori $[[IMM]], $[[IMM]], 32766377; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[IMM]], $4378; FIXME: We can do better than this by using selccz to choose between -0 and -2379; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]380; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]381; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]382 383define i32 @slti3(i32 signext %a) {384entry:385 %cmp = icmp sgt i32 %a, -32770386 %cond = select i1 %cmp, i32 3, i32 5387 ret i32 %cond388}389 390; 64-bit patterns.391 392; ALL-LABEL: slti64_0:393 394; 32-CMOV-DAG: slt $[[CC:[0-9]+]], $zero, $4395; 32-CMOV-DAG: addiu $[[I32766:[0-9]+]], $zero, 32766396; 32-CMOV-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5397; 32-CMOV-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4398; 32-CMOV-DAG: addiu $[[I5:[0-9]+]], $zero, 5399; 32-CMOV-DAG: addiu $[[I4:3]], $zero, 4400; 32-CMOV-DAG: movn $[[I4]], $[[I5]], $[[CC]]401; 32-CMOV-DAG: addiu $2, $zero, 0402 403; 32-CMP-DAG: slt $[[CC0:[0-9]+]], $zero, $4404; 32-CMP-DAG: addiu $[[I32766:[0-9]+]], $zero, 32766405; 32-CMP-DAG: sltu $[[CC1:[0-9]+]], $[[I32766]], $5406; 32-CMP-DAG: selnez $[[CC2:[0-9]+]], $[[CC0]], $4407; 32-CMP-DAG: seleqz $[[CC3:[0-9]+]], $[[CC1]], $4408; 32-CMP: or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]]409; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5410; 32-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4411; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[CC]]412; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[CC]]413; 32-CMP-DAG: or $3, $[[T1]], $[[T0]]414; 32-CMP-DAG: addiu $2, $zero, 0415 416; 64-CMOV-DAG: addiu $[[I5:[0-9]+]], $zero, 5417; 64-CMOV-DAG: addiu $[[I4:2]], $zero, 4418; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767419; 64-CMOV-DAG: movz $[[I4]], $[[I5]], $[[R0]]420 421; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5422; 64-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4423; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, 32767424; FIXME: We can do better than this by adding/subtracting the result of slti425; to/from one of the constants.426; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I5]], $[[R0]]427; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]428; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]429 430define i64 @slti64_0(i64 %a) {431entry:432 %cmp = icmp sgt i64 %a, 32766433 %conv = select i1 %cmp, i64 5, i64 4434 ret i64 %conv435}436 437; ALL-LABEL: slti64_1:438 439; 32-CMOV-DAG: slt $[[CC:[0-9]+]], $zero, $4440; 32-CMOV-DAG: addiu $[[I32766:[0-9]+]], $zero, 32767441; 32-CMOV-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5442; 32-CMOV-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4443; 32-CMOV-DAG: addiu $[[I5:[0-9]+]], $zero, 5444; 32-CMOV-DAG: addiu $[[I4:3]], $zero, 4445; 32-CMOV-DAG: movn $[[I4]], $[[I5]], $[[CC]]446; 32-CMOV-DAG: addiu $2, $zero, 0447 448; 32-CMP-DAG: slt $[[CC0:[0-9]+]], $zero, $4449; 32-CMP-DAG: addiu $[[I32766:[0-9]+]], $zero, 32767450; 32-CMP-DAG: sltu $[[CC1:[0-9]+]], $[[I32766]], $5451; 32-CMP-DAG: selnez $[[CC2:[0-9]+]], $[[CC0]], $4452; 32-CMP-DAG: seleqz $[[CC3:[0-9]+]], $[[CC1]], $4453; 32-CMP: or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]]454; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5455; 32-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4456; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[CC]]457; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[CC]]458; 32-CMP-DAG: or $3, $[[T1]], $[[T0]]459; 32-CMP-DAG: addiu $2, $zero, 0460 461; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5462; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4463; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767464; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4465; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]466 467; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5468; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4469; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767470; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4471; FIXME: We can do better than this by using selccz to choose between -0 and -2472; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]473; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]474; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]475 476define i64 @slti64_1(i64 %a) {477entry:478 %cmp = icmp sgt i64 %a, 32767479 %conv = select i1 %cmp, i64 5, i64 4480 ret i64 %conv481}482 483; ALL-LABEL: slti64_2:484 485; FIXME: The 32-bit versions of this test are too complicated to reasonably486; match at the moment. They do show some missing optimizations though487; such as:488; (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)489 490; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3491; 64-CMOV-DAG: addiu $[[I4:2]], $zero, 4492; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768493; 64-CMOV-DAG: movz $[[I4]], $[[I3]], $[[R0]]494 495; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3496; 64-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4497; 64-CMP-DAG: slti $[[R0:[0-9]+]], $4, -32768498; FIXME: We can do better than this by adding/subtracting the result of slti499; to/from one of the constants.500; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]501; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]502; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]503 504define i64 @slti64_2(i64 %a) {505entry:506 %cmp = icmp sgt i64 %a, -32769507 %conv = select i1 %cmp, i64 3, i64 4508 ret i64 %conv509}510 511; ALL-LABEL: slti64_3:512 513; FIXME: The 32-bit versions of this test are too complicated to reasonably514; match at the moment. They do show some missing optimizations though515; such as:516; (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)517 518; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5519; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4520 521 522; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535523; 64-CMOV-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766524; 64-CMOV-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4525; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R3]]526 527; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5528; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4529 530; 64-CMP-DAG: lui $[[R1:[0-9]+]], 65535531; 64-CMP-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766532; 64-CMP-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4533; FIXME: We can do better than this by using selccz to choose between -0 and -2534; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R3]]535; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R3]]536; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]537 538define i64 @slti64_3(i64 %a) {539entry:540 %cmp = icmp sgt i64 %a, -32770541 %conv = select i1 %cmp, i64 5, i64 4542 ret i64 %conv543}544 545; sltiu instructions.546 547; ALL-LABEL: sltiu0:548 549; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3550; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5551; 32-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, 32767552; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]553 554; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3555; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5556; 32-CMP-DAG: sltiu $[[R0:[0-9]+]], $4, 32767557; FIXME: We can do better than this by using selccz to choose between +0 and +2558; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]559; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]560; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]561 562; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3563; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5564; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, 32767565; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]566 567; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3568; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5569; 64-CMP-DAG: sltiu $[[R0:[0-9]+]], $4, 32767570; FIXME: We can do better than this by using selccz to choose between +0 and +2571; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]572; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]573; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]574 575define i32 @sltiu0(i32 signext %a) {576entry:577 %cmp = icmp ugt i32 %a, 32766578 %cond = select i1 %cmp, i32 3, i32 5579 ret i32 %cond580}581 582; ALL-LABEL: sltiu1:583 584; 32-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7585; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5586; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], $zero, 32767587; 32-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4588; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]589 590; 32-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7591; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5592; 32-CMP-DAG: addiu $[[I32767:[0-9]+]], $zero, 32767593; 32-CMP-DAG: sltu $[[R0:[0-9]+]], $[[I32767]], $4594; FIXME: We can do better than this by using selccz to choose between -0 and -2595; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I7]], $[[R0]]596; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]597; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]598 599; 64-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7600; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5601; 64-CMOV-DAG: addiu $[[R1:[0-9]+]], $zero, 32767602; 64-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4603; 64-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]604 605; 64-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7606; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5607; 64-CMP-DAG: addiu $[[R1:[0-9]+]], $zero, 32767608; 64-CMP-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4609; FIXME: We can do better than this by using selccz to choose between -0 and -2610; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I7]], $[[R0]]611; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]612; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]613 614define i32 @sltiu1(i32 signext %a) {615entry:616 %cmp = icmp ugt i32 %a, 32767617 %cond = select i1 %cmp, i32 7, i32 5618 ret i32 %cond619}620 621; ALL-LABEL: sltiu2:622 623; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3624; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5625; 32-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768626; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]627 628; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3629; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5630; 32-CMP-DAG: sltiu $[[R0:[0-9]+]], $4, -32768631; FIXME: We can do better than this by using selccz to choose between +0 and +2632; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]633; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]634; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]635 636; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3637; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5638; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768639; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]640 641; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3642; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5643; 64-CMP-DAG: sltiu $[[R0:[0-9]+]], $4, -32768644; FIXME: We can do better than this by using selccz to choose between +0 and +2645; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]646; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]647; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]648 649define i32 @sltiu2(i32 signext %a) {650entry:651 %cmp = icmp ugt i32 %a, -32769652 %cond = select i1 %cmp, i32 3, i32 5653 ret i32 %cond654}655 656; ALL-LABEL: sltiu3:657 658; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3659; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5660; 32-CMOV-DAG: lui $[[R1:[0-9]+]], 65535661; 32-CMOV-DAG: ori $[[R1]], $[[R1]], 32766662; 32-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4663; 32-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]]664 665; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3666; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5667; 32-CMP-DAG: lui $[[IMM:[0-9]+]], 65535668; 32-CMP-DAG: ori $[[IMM]], $[[IMM]], 32766669; 32-CMP-DAG: sltu $[[R0:[0-9]+]], $[[I32767]], $4670; FIXME: We can do better than this by using selccz to choose between -0 and -2671; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]672; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]673; 32-CMP-DAG: or $2, $[[T0]], $[[T1]]674 675; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3676; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5677; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535678; 64-CMOV-DAG: ori $[[R1]], $[[R1]], 32766679; 64-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4680; 64-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]]681 682; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3683; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5684; 64-CMP-DAG: lui $[[IMM:[0-9]+]], 65535685; 64-CMP-DAG: ori $[[IMM]], $[[IMM]], 32766686; 64-CMP-DAG: sltu $[[R0:[0-9]+]], $[[IMM]], $4687; FIXME: We can do better than this by using selccz to choose between -0 and -2688; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I3]], $[[R0]]689; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]690; 64-CMP-DAG: or $2, $[[T0]], $[[T1]]691 692define i32 @sltiu3(i32 signext %a) {693entry:694 %cmp = icmp ugt i32 %a, -32770695 %cond = select i1 %cmp, i32 3, i32 5696 ret i32 %cond697}698 699; Check if700; (select (setxx a, N), x, x-1) or701; (select (setxx a, N), x-1, x)702; doesn't generate conditional moves703; for constant operands whose difference is |1|704 705define i32 @slti4(i32 signext %a) nounwind readnone {706 %1 = icmp slt i32 %a, 7707 %2 = select i1 %1, i32 4, i32 3708 ret i32 %2709}710 711; ALL-LABEL: slti4:712 713; 32-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7714; 32-CMOV-DAG: addiu $2, [[R1]], 3715; 32-CMOV-NOT: movn716 717; 32-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7718; 32-CMP-DAG: addiu $2, [[R1]], 3719; 32-CMP-NOT: seleqz720; 32-CMP-NOT: selnez721 722; 64-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7723; 64-CMOV-DAG: addiu $2, [[R1]], 3724; 64-CMOV-NOT: movn725 726; 64-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7727; 64-CMP-DAG: addiu $2, [[R1]], 3728; 64-CMP-NOT: seleqz729; 64-CMP-NOT: selnez730 731define i32 @slti5(i32 signext %a) nounwind readnone {732 %1 = icmp slt i32 %a, 7733 %2 = select i1 %1, i32 -3, i32 -4734 ret i32 %2735}736 737; ALL-LABEL: slti5:738 739; 32-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7740; 32-CMOV-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4741; 32-CMOV-NOT: movn742 743; 32-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7744; 32-CMP-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4745; 32-CMP-NOT: seleqz746; 32-CMP-NOT: selnez747 748; 64-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7749; 64-CMOV-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4750; 64-CMOV-NOT: movn751 752; 64-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7753; 64-CMP-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4754; 64-CMP-NOT: seleqz755; 64-CMP-NOT: selnez756 757define i32 @slti6(i32 signext %a) nounwind readnone {758 %1 = icmp slt i32 %a, 7759 %2 = select i1 %1, i32 3, i32 4760 ret i32 %2761}762 763; ALL-LABEL: slti6:764 765; ALL-DAG: addiu [[R1:\$[0-9]+]], $zero, 6766; ALL-DAG: slt [[R1]], [[R1]], $4767; ALL-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3768; ALL-NOT: movn769; ALL-NOT: seleqz770; ALL-NOT: selnez771