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1# RUN: llc -mtriple=mips64 -mcpu=mips64r6 -start-after=block-placement -o - %s | FileCheck %s2 3# Check that MipsHazardSchedule sees through basic blocks with transient instructions.4# The mir code in this file isn't representative of the llvm-ir.5 6--- |7 ; ModuleID = 'test.ll'8 source_filename = "test.c"9 target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"10 target triple = "mips64-img-linux-gnu"11 12 ; Function Attrs: nounwind13 define i32 @f(i32 signext %a) {14 entry:15 %retval = alloca i32, align 416 %a.addr = alloca i32, align 417 store i32 %a, ptr %a.addr, align 418 %0 = load i32, ptr %a.addr, align 419 %cmp = icmp sgt i32 %0, 520 br i1 %cmp, label %if.then, label %if.else21 22 if.then: ; preds = %entry23 %1 = load i32, ptr %a.addr, align 424 %2 = load i32, ptr %a.addr, align 425 %add = add nsw i32 %1, %226 store i32 %add, ptr %retval, align 427 br label %return28 29 if.else: ; preds = %entry30 %3 = load i32, ptr %a.addr, align 431 %call = call i32 @g(i32 signext %3)32 store i32 %call, ptr %retval, align 433 br label %return34 35 return: ; preds = %if.else, %if.then36 %4 = load i32, ptr %retval, align 437 ret i32 %438 }39 40 declare i32 @g(i32 signext)41 42 ; Function Attrs: nounwind43 declare void @llvm.stackprotector(ptr, ptr)44 45 !llvm.ident = !{!0}46 47 !0 = !{!"clang version 4.0.0 "}48 49...50---51# CHECK-LABEL: f:52# CHECK: bgtzc53# CHECK-NEXT: nop54# CHECK: bltzc55# CHECK-NEXT: nop56# CHECK: blezc57name: f58alignment: 859exposesReturnsTwice: false60legalized: false61regBankSelected: false62selected: false63tracksRegLiveness: true64liveins:65 - { reg: '$a0_64' }66 - { reg: '$t9_64' }67calleeSavedRegisters: [ '$fp', '$gp', '$ra', '$d12', '$d13', '$d14', '$d15',68 '$f24', '$f25', '$f26', '$f27', '$f28', '$f29',69 '$f30', '$f31', '$fp_64', '$f_hi24', '$f_hi25',70 '$f_hi26', '$f_hi27', '$f_hi28', '$f_hi29', '$f_hi30',71 '$f_hi31', '$gp_64', '$ra_64', '$s0', '$s1', '$s2',72 '$s3', '$s4', '$s5', '$s6', '$s7', '$d24_64', '$d25_64',73 '$d26_64', '$d27_64', '$d28_64', '$d29_64', '$d30_64',74 '$d31_64', '$s0_64', '$s1_64', '$s2_64', '$s3_64',75 '$s4_64', '$s5_64', '$s6_64', '$s7_64' ]76frameInfo:77 isFrameAddressTaken: false78 isReturnAddressTaken: false79 hasStackMap: false80 hasPatchPoint: false81 stackSize: 3282 offsetAdjustment: 083 maxAlignment: 884 adjustsStack: true85 hasCalls: true86 maxCallFrameSize: 087 hasOpaqueSPAdjustment: false88 hasVAStart: false89 hasMustTailInVarArgFunc: false90stack:91 - { id: 0, name: retval, offset: -28, size: 4, alignment: 4 }92 - { id: 1, name: a.addr, offset: -32, size: 4, alignment: 4 }93 - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '$ra_64' }94 - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '$fp_64' }95 - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$gp_64' }96body: |97 bb.0.entry:98 successors: %bb.1.if.then(0x40000000), %bb.5.if.else(0x40000000)99 liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64100 101 $sp_64 = DADDiu $sp_64, -32102 CFI_INSTRUCTION def_cfa_offset 32103 SD killed $ra_64, $sp_64, 24 :: (store (s64) into %stack.2)104 SD killed $fp_64, $sp_64, 16 :: (store (s64) into %stack.3)105 SD killed $gp_64, $sp_64, 8 :: (store (s64) into %stack.4)106 CFI_INSTRUCTION offset $ra_64, -8107 CFI_INSTRUCTION offset $fp_64, -16108 CFI_INSTRUCTION offset $gp_64, -24109 CFI_INSTRUCTION def_cfa_register $fp_64110 $at_64 = LUi64 @f111 $v0_64 = DADDu killed $at_64, $t9_64112 SW $a0, $sp_64, 0 :: (store (s32) into %ir.a.addr)113 BGTZC $a0, %bb.5.if.else, implicit-def $at114 115 bb.1.if.then:116 successors: %bb.6.return(0x40000000), %bb.2.if.then(0x40000000)117 liveins: $a0118 119 BLTZC $a0, %bb.6.return, implicit-def $at120 121 bb.2.if.then:122 successors: %bb.3.if.else(0x80000000)123 $t8 = IMPLICIT_DEF124 125 bb.3.if.else:126 successors: %bb.6.return(0x40000000), %bb.4.if.else(0x40000000)127 liveins: $t8128 129 BLEZC $t8, %bb.6.return, implicit-def $at130 131 bb.4.if.else:132 successors: %bb.6.return(0x80000000)133 liveins: $t8134 135 $at = LW $sp_64, 0 :: (dereferenceable load (s32) from %ir.a.addr)136 $at = ADDu killed $at, $t8137 SW killed $at, $sp_64, 4 :: (store (s32) into %ir.retval)138 J %bb.6.return, implicit-def dead $at139 140 bb.5.if.else:141 successors: %bb.6.return(0x80000000)142 liveins: $v0_64143 144 $gp_64 = DADDiu killed $v0_64, @f145 $a0_64 = LW64 $sp_64, 0 :: (dereferenceable load (s32) from %ir.a.addr)146 $t9_64 = LD $gp_64, @g :: (load (s64) from call-entry @g)147 JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0148 SW killed $v0, $sp_64, 4 :: (store (s32) into %ir.retval)149 150 bb.6.return:151 $v0 = LW $sp_64, 4 :: (dereferenceable load (s32) from %ir.retval)152 $gp_64 = LD $sp_64, 8 :: (load (s64) from %stack.4)153 $fp_64 = LD $sp_64, 16 :: (load (s64) from %stack.3)154 $ra_64 = LD $sp_64, 24 :: (load (s64) from %stack.2)155 $sp_64 = DADDiu $sp_64, 32156 PseudoReturn64 $ra_64157 158...159