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1# RUN: llc -mtriple=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s2 3# Check that empty blocks in the cfg don't cause the mips hazard scheduler to4# crash and that the nop is inserted correctly.5 6# CHECK: blezc7# CHECK: nop8# CHECK: # %bb.1:9# CHECK: .insn10# CHECK: # %bb.2:11# CHECK: .insn12# CHECK: # %bb.3:13# CHECK: jal14 15--- |16 ; ModuleID = '<stdin>'17 source_filename = "<stdin>"18 target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"19 20 declare i32 @k()21 22 declare void @f(i32)23 24 define void @l5() {25 entry:26 %call = tail call i32 @k()27 %cmp = icmp sgt i32 %call, 028 br i1 %cmp, label %if.then, label %if.end29 30 if.then: ; preds = %entry31 tail call void @f(i32 signext 2)32 br label %if.end33 34 if.end: ; preds = %if.then, %entry35 ret void36 }37 38---39name: l540alignment: 441exposesReturnsTwice: false42legalized: false43regBankSelected: false44selected: false45tracksRegLiveness: true46frameInfo:47 isFrameAddressTaken: false48 isReturnAddressTaken: false49 hasStackMap: false50 hasPatchPoint: false51 stackSize: 2452 offsetAdjustment: 053 maxAlignment: 454 adjustsStack: true55 hasCalls: true56 maxCallFrameSize: 1657 hasOpaqueSPAdjustment: false58 hasVAStart: false59 hasMustTailInVarArgFunc: false60stack:61 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$ra' }62body: |63 bb.0.entry:64 successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000)65 liveins: $ra66 67 $sp = ADDiu $sp, -2468 CFI_INSTRUCTION def_cfa_offset 2469 SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)70 CFI_INSTRUCTION offset $ra_64, -471 JAL @k, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def $v072 BLEZ $v0, %bb.4.if.end, implicit-def $at73 74 bb.1.if.then:75 successors: %bb.2.if.then(0x80000000)76 77 bb.2.if.then:78 successors: %bb.3.if.then(0x80000000)79 80 bb.3.if.then:81 successors: %bb.4.if.end(0x80000000)82 83 $a0 = ADDiu $zero, 284 JAL @f, csr_o32_fp64, implicit-def dead $ra, implicit killed $a0, implicit-def $sp85 86 bb.4.if.end:87 $ra = LW $sp, 20 :: (load (s32) from %stack.0)88 $sp = ADDiu $sp, 2489 PseudoReturn undef $ra90 91...92