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1; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s2 3; Currently, the following IR assembly generates a KILL instruction between4; the bitwise-and instruction and the return instruction. We verify that the5; delay slot filler ignores such KILL instructions by filling the slot of the6; return instruction properly.7define signext i32 @f1(i32 signext %a, i32 signext %b) {8entry:9 ; CHECK: jr $ra10 ; CHECK-NEXT: and $2, $4, $511 12 %r = and i32 %a, %b13 ret i32 %r14}15