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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \3; RUN: -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R24; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mcpu=mips32r2 < %s -o - \5; RUN: | FileCheck %s -check-prefix=MIPS32R26; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mattr=mips16 < %s -o - \7; RUN: | FileCheck %s -check-prefix=MIPS168; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \9; RUN: -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N3210 11; #include <stdint.h>12; #include <stdio.h>13; struct cvmx_buf_ptr {14 15; struct {16; unsigned long long addr :37;17; unsigned long long addr1 :15;18; unsigned int length:14;19; uint64_t total_bytes:16;20; uint64_t segs : 6;21; } s;22; }23;24; unsigned long long foo(volatile struct cvmx_buf_ptr bufptr) {25; bufptr.s.addr = 123;26; bufptr.s.segs = 4;27; bufptr.s.length = 5;28; bufptr.s.total_bytes = bufptr.s.length;29; return bufptr.s.addr;30; }31 32; Testing of selection INS/DINS instruction33 34define i64 @f123(i64 inreg %bufptr.coerce0, i64 inreg %bufptr.coerce1) local_unnamed_addr #0 {35; MIPS64R2-LABEL: f123:36; MIPS64R2: # %bb.0: # %entry37; MIPS64R2-NEXT: daddiu $sp, $sp, -1638; MIPS64R2-NEXT: .cfi_def_cfa_offset 1639; MIPS64R2-NEXT: sd $4, 8($sp)40; MIPS64R2-NEXT: sd $5, 0($sp)41; MIPS64R2-NEXT: daddiu $1, $zero, 12342; MIPS64R2-NEXT: ld $2, 8($sp)43; MIPS64R2-NEXT: dinsm $2, $1, 27, 3744; MIPS64R2-NEXT: sd $2, 8($sp)45; MIPS64R2-NEXT: daddiu $1, $zero, 446; MIPS64R2-NEXT: ld $2, 0($sp)47; MIPS64R2-NEXT: dinsm $2, $1, 28, 648; MIPS64R2-NEXT: daddiu $1, $zero, 549; MIPS64R2-NEXT: sd $2, 0($sp)50; MIPS64R2-NEXT: ld $2, 0($sp)51; MIPS64R2-NEXT: dinsu $2, $1, 50, 1452; MIPS64R2-NEXT: sd $2, 0($sp)53; MIPS64R2-NEXT: ld $1, 0($sp)54; MIPS64R2-NEXT: dsrl $1, $1, 5055; MIPS64R2-NEXT: ld $2, 0($sp)56; MIPS64R2-NEXT: dinsu $2, $1, 34, 1657; MIPS64R2-NEXT: sd $2, 0($sp)58; MIPS64R2-NEXT: ld $1, 8($sp)59; MIPS64R2-NEXT: dsrl $2, $1, 2760; MIPS64R2-NEXT: jr $ra61; MIPS64R2-NEXT: daddiu $sp, $sp, 1662;63; MIPS32R2-LABEL: f123:64; MIPS32R2: # %bb.0: # %entry65; MIPS32R2-NEXT: addiu $sp, $sp, -1666; MIPS32R2-NEXT: .cfi_def_cfa_offset 1667; MIPS32R2-NEXT: lw $1, 8($sp)68; MIPS32R2-NEXT: lw $1, 12($sp)69; MIPS32R2-NEXT: addiu $2, $zero, 370; MIPS32R2-NEXT: sw $2, 8($sp)71; MIPS32R2-NEXT: ext $1, $1, 0, 2772; MIPS32R2-NEXT: lui $2, 5529673; MIPS32R2-NEXT: or $1, $1, $274; MIPS32R2-NEXT: sw $1, 12($sp)75; MIPS32R2-NEXT: addiu $1, $zero, -476; MIPS32R2-NEXT: lw $2, 0($sp)77; MIPS32R2-NEXT: and $1, $2, $178; MIPS32R2-NEXT: lw $2, 4($sp)79; MIPS32R2-NEXT: sw $1, 0($sp)80; MIPS32R2-NEXT: ext $1, $2, 0, 2881; MIPS32R2-NEXT: lui $2, 1638482; MIPS32R2-NEXT: or $1, $1, $283; MIPS32R2-NEXT: lui $2, 2084; MIPS32R2-NEXT: sw $1, 4($sp)85; MIPS32R2-NEXT: lw $1, 0($sp)86; MIPS32R2-NEXT: lw $3, 4($sp)87; MIPS32R2-NEXT: sw $3, 4($sp)88; MIPS32R2-NEXT: ext $1, $1, 0, 1889; MIPS32R2-NEXT: or $1, $1, $290; MIPS32R2-NEXT: sw $1, 0($sp)91; MIPS32R2-NEXT: lw $1, 4($sp)92; MIPS32R2-NEXT: lw $1, 0($sp)93; MIPS32R2-NEXT: lw $2, 0($sp)94; MIPS32R2-NEXT: lw $3, 4($sp)95; MIPS32R2-NEXT: sw $3, 4($sp)96; MIPS32R2-NEXT: srl $1, $1, 1897; MIPS32R2-NEXT: ins $2, $1, 2, 1698; MIPS32R2-NEXT: sw $2, 0($sp)99; MIPS32R2-NEXT: lw $1, 8($sp)100; MIPS32R2-NEXT: sll $2, $1, 5101; MIPS32R2-NEXT: lw $3, 12($sp)102; MIPS32R2-NEXT: srl $3, $3, 27103; MIPS32R2-NEXT: or $3, $3, $2104; MIPS32R2-NEXT: srl $2, $1, 27105; MIPS32R2-NEXT: jr $ra106; MIPS32R2-NEXT: addiu $sp, $sp, 16107;108; MIPS16-LABEL: f123:109; MIPS16: # %bb.0: # %entry110; MIPS16-NEXT: save 16 # 16 bit inst111; MIPS16-EMPTY:112; MIPS16-NEXT: .cfi_def_cfa_offset 16113; MIPS16-NEXT: lw $2, 8($sp)114; MIPS16-NEXT: lw $2, 12($sp)115; MIPS16-NEXT: li $3, 3116; MIPS16-NEXT: sw $3, 8($sp)117; MIPS16-NEXT: lw $3, $CPI0_0 # 16 bit inst118; MIPS16-NEXT: and $3, $2119; MIPS16-NEXT: lw $2, $CPI0_1 # 16 bit inst120; MIPS16-NEXT: or $2, $3121; MIPS16-NEXT: sw $2, 12($sp)122; MIPS16-NEXT: move $2, $zero123; MIPS16-NEXT: addiu $2, -4124; MIPS16-NEXT: lw $3, 0($sp)125; MIPS16-NEXT: and $3, $2126; MIPS16-NEXT: lw $2, 4($sp)127; MIPS16-NEXT: sw $3, 0($sp)128; MIPS16-NEXT: lw $3, $CPI0_2 # 16 bit inst129; MIPS16-NEXT: and $3, $2130; MIPS16-NEXT: lw $2, $CPI0_3 # 16 bit inst131; MIPS16-NEXT: or $2, $3132; MIPS16-NEXT: sw $2, 4($sp)133; MIPS16-NEXT: lw $2, 0($sp)134; MIPS16-NEXT: lw $3, 4($sp)135; MIPS16-NEXT: sw $3, 4($sp)136; MIPS16-NEXT: lw $3, $CPI0_4 # 16 bit inst137; MIPS16-NEXT: and $3, $2138; MIPS16-NEXT: lw $2, $CPI0_5 # 16 bit inst139; MIPS16-NEXT: or $2, $3140; MIPS16-NEXT: sw $2, 0($sp)141; MIPS16-NEXT: lw $2, 4($sp)142; MIPS16-NEXT: lw $2, 0($sp)143; MIPS16-NEXT: lw $3, 0($sp)144; MIPS16-NEXT: lw $4, 4($sp)145; MIPS16-NEXT: sw $4, 4($sp)146; MIPS16-NEXT: srl $2, $2, 16147; MIPS16-NEXT: li $4, 65532148; MIPS16-NEXT: and $4, $2149; MIPS16-NEXT: lw $2, $CPI0_6 # 16 bit inst150; MIPS16-NEXT: and $2, $3151; MIPS16-NEXT: or $2, $4152; MIPS16-NEXT: sw $2, 0($sp)153; MIPS16-NEXT: lw $2, 12($sp)154; MIPS16-NEXT: srl $2, $2, 27155; MIPS16-NEXT: lw $4, 8($sp)156; MIPS16-NEXT: sll $3, $4, 5157; MIPS16-NEXT: or $3, $2158; MIPS16-NEXT: srl $2, $4, 27159; MIPS16-NEXT: restore 16 # 16 bit inst160; MIPS16-EMPTY:161; MIPS16-NEXT: jrc $ra162; MIPS16-NEXT: .p2align 2163; MIPS16-NEXT: # %bb.1:164; MIPS16-NEXT: $CPI0_0:165; MIPS16-NEXT: .4byte 134217727 # 0x7ffffff166; MIPS16-NEXT: $CPI0_1:167; MIPS16-NEXT: .4byte 3623878656 # 0xd8000000168; MIPS16-NEXT: $CPI0_2:169; MIPS16-NEXT: .4byte 268435455 # 0xfffffff170; MIPS16-NEXT: $CPI0_3:171; MIPS16-NEXT: .4byte 1073741824 # 0x40000000172; MIPS16-NEXT: $CPI0_4:173; MIPS16-NEXT: .4byte 262143 # 0x3ffff174; MIPS16-NEXT: $CPI0_5:175; MIPS16-NEXT: .4byte 1310720 # 0x140000176; MIPS16-NEXT: $CPI0_6:177; MIPS16-NEXT: .4byte 4294705155 # 0xfffc0003178;179; MIPS64R2N32-LABEL: f123:180; MIPS64R2N32: # %bb.0: # %entry181; MIPS64R2N32-NEXT: addiu $sp, $sp, -16182; MIPS64R2N32-NEXT: .cfi_def_cfa_offset 16183; MIPS64R2N32-NEXT: sd $4, 8($sp)184; MIPS64R2N32-NEXT: sd $5, 0($sp)185; MIPS64R2N32-NEXT: daddiu $1, $zero, 123186; MIPS64R2N32-NEXT: ld $2, 8($sp)187; MIPS64R2N32-NEXT: dinsm $2, $1, 27, 37188; MIPS64R2N32-NEXT: sd $2, 8($sp)189; MIPS64R2N32-NEXT: daddiu $1, $zero, 4190; MIPS64R2N32-NEXT: ld $2, 0($sp)191; MIPS64R2N32-NEXT: dinsm $2, $1, 28, 6192; MIPS64R2N32-NEXT: daddiu $1, $zero, 5193; MIPS64R2N32-NEXT: sd $2, 0($sp)194; MIPS64R2N32-NEXT: ld $2, 0($sp)195; MIPS64R2N32-NEXT: dinsu $2, $1, 50, 14196; MIPS64R2N32-NEXT: sd $2, 0($sp)197; MIPS64R2N32-NEXT: ld $1, 0($sp)198; MIPS64R2N32-NEXT: dsrl $1, $1, 50199; MIPS64R2N32-NEXT: ld $2, 0($sp)200; MIPS64R2N32-NEXT: dinsu $2, $1, 34, 16201; MIPS64R2N32-NEXT: sd $2, 0($sp)202; MIPS64R2N32-NEXT: ld $1, 8($sp)203; MIPS64R2N32-NEXT: dsrl $2, $1, 27204; MIPS64R2N32-NEXT: jr $ra205; MIPS64R2N32-NEXT: addiu $sp, $sp, 16206entry:207 %bufptr.sroa.0 = alloca i64, align 8208 %bufptr.sroa.4 = alloca i64, align 8209 store i64 %bufptr.coerce0, ptr %bufptr.sroa.0, align 8210 store i64 %bufptr.coerce1, ptr %bufptr.sroa.4, align 8211 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load = load volatile i64, ptr %bufptr.sroa.0, align 8212 %bf.clear = and i64 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load, 134217727213 %bf.set = or i64 %bf.clear, 16508780544214 store volatile i64 %bf.set, ptr %bufptr.sroa.0, align 8215 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load2 = load volatile i64, ptr %bufptr.sroa.4, align 8216 %bf.clear3 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load2, -16911433729217 %bf.set4 = or i64 %bf.clear3, 1073741824218 store volatile i64 %bf.set4, ptr %bufptr.sroa.4, align 8219 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load6 = load volatile i64, ptr %bufptr.sroa.4, align 8220 %bf.clear7 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load6, 1125899906842623221 %bf.set8 = or i64 %bf.clear7, 5629499534213120222 store volatile i64 %bf.set8, ptr %bufptr.sroa.4, align 8223 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load11 = load volatile i64, ptr %bufptr.sroa.4, align 8224 %bf.lshr = lshr i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load11, 50225 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load13 = load volatile i64, ptr %bufptr.sroa.4, align 8226 %bf.shl = shl nuw nsw i64 %bf.lshr, 34227 %bf.clear14 = and i64 %bufptr.sroa.4.0.bufptr.sroa.4.0.bufptr.sroa.4.8.bf.load13, -1125882726973441228 %bf.set15 = or i64 %bf.clear14, %bf.shl229 store volatile i64 %bf.set15, ptr %bufptr.sroa.4, align 8230 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load17 = load volatile i64, ptr %bufptr.sroa.0, align 8231 %bf.lshr18 = lshr i64 %bufptr.sroa.0.0.bufptr.sroa.0.0.bufptr.sroa.0.0.bf.load17, 27232 ret i64 %bf.lshr18233}234 235; int foo(volatile int x) {236; int y = x;237; y = y & -4;238; x = y | 8;239; return y;240; }241 242define i32 @foo(i32 signext %x) {243; MIPS64R2-LABEL: foo:244; MIPS64R2: # %bb.0: # %entry245; MIPS64R2-NEXT: daddiu $sp, $sp, -16246; MIPS64R2-NEXT: .cfi_def_cfa_offset 16247; MIPS64R2-NEXT: sw $4, 12($sp)248; MIPS64R2-NEXT: addiu $1, $zero, -4249; MIPS64R2-NEXT: lw $2, 12($sp)250; MIPS64R2-NEXT: and $2, $2, $1251; MIPS64R2-NEXT: ori $1, $2, 8252; MIPS64R2-NEXT: sw $1, 12($sp)253; MIPS64R2-NEXT: jr $ra254; MIPS64R2-NEXT: daddiu $sp, $sp, 16255;256; MIPS32R2-LABEL: foo:257; MIPS32R2: # %bb.0: # %entry258; MIPS32R2-NEXT: addiu $sp, $sp, -8259; MIPS32R2-NEXT: .cfi_def_cfa_offset 8260; MIPS32R2-NEXT: sw $4, 4($sp)261; MIPS32R2-NEXT: addiu $1, $zero, -4262; MIPS32R2-NEXT: lw $2, 4($sp)263; MIPS32R2-NEXT: and $2, $2, $1264; MIPS32R2-NEXT: ori $1, $2, 8265; MIPS32R2-NEXT: sw $1, 4($sp)266; MIPS32R2-NEXT: jr $ra267; MIPS32R2-NEXT: addiu $sp, $sp, 8268;269; MIPS16-LABEL: foo:270; MIPS16: # %bb.0: # %entry271; MIPS16-NEXT: save 8 # 16 bit inst272; MIPS16-EMPTY:273; MIPS16-NEXT: .cfi_def_cfa_offset 8274; MIPS16-NEXT: sw $4, 4($sp)275; MIPS16-NEXT: move $3, $zero276; MIPS16-NEXT: addiu $3, -4277; MIPS16-NEXT: lw $2, 4($sp)278; MIPS16-NEXT: and $2, $3279; MIPS16-NEXT: li $3, 8280; MIPS16-NEXT: or $3, $2281; MIPS16-NEXT: sw $3, 4($sp)282; MIPS16-NEXT: restore 8 # 16 bit inst283; MIPS16-EMPTY:284; MIPS16-NEXT: jrc $ra285;286; MIPS64R2N32-LABEL: foo:287; MIPS64R2N32: # %bb.0: # %entry288; MIPS64R2N32-NEXT: addiu $sp, $sp, -16289; MIPS64R2N32-NEXT: .cfi_def_cfa_offset 16290; MIPS64R2N32-NEXT: sw $4, 12($sp)291; MIPS64R2N32-NEXT: addiu $1, $zero, -4292; MIPS64R2N32-NEXT: lw $2, 12($sp)293; MIPS64R2N32-NEXT: and $2, $2, $1294; MIPS64R2N32-NEXT: ori $1, $2, 8295; MIPS64R2N32-NEXT: sw $1, 12($sp)296; MIPS64R2N32-NEXT: jr $ra297; MIPS64R2N32-NEXT: addiu $sp, $sp, 16298entry:299 %x.addr = alloca i32, align 4300 store volatile i32 %x, ptr %x.addr, align 4301 %x.addr.0.x.addr.0. = load volatile i32, ptr %x.addr, align 4302 %and = and i32 %x.addr.0.x.addr.0., -4303 %or = or i32 %and, 8304 store volatile i32 %or, ptr %x.addr, align 4305 ret i32 %and306}307 308define i32 @pr125954(i32 %arg, i1 %c) {309; MIPS64R2-LABEL: pr125954:310; MIPS64R2: # %bb.0:311; MIPS64R2-NEXT: sll $1, $4, 0312; MIPS64R2-NEXT: addiu $2, $zero, -1313; MIPS64R2-NEXT: move $3, $1314; MIPS64R2-NEXT: ins $3, $2, 8, 24315; MIPS64R2-NEXT: andi $2, $1, 255316; MIPS64R2-NEXT: sll $1, $5, 0317; MIPS64R2-NEXT: andi $1, $1, 1318; MIPS64R2-NEXT: jr $ra319; MIPS64R2-NEXT: movn $2, $3, $1320;321; MIPS32R2-LABEL: pr125954:322; MIPS32R2: # %bb.0:323; MIPS32R2-NEXT: andi $2, $4, 255324; MIPS32R2-NEXT: addiu $1, $zero, -256325; MIPS32R2-NEXT: or $1, $2, $1326; MIPS32R2-NEXT: andi $3, $5, 1327; MIPS32R2-NEXT: jr $ra328; MIPS32R2-NEXT: movn $2, $1, $3329;330; MIPS16-LABEL: pr125954:331; MIPS16: # %bb.0:332; MIPS16-NEXT: li $6, 1333; MIPS16-NEXT: and $6, $5334; MIPS16-NEXT: li $2, 255335; MIPS16-NEXT: and $2, $4336; MIPS16-NEXT: move $3, $zero337; MIPS16-NEXT: beqz $6, $BB2_2 # 16 bit inst338; MIPS16-NEXT: # %bb.1:339; MIPS16-NEXT: addiu $3, -256340; MIPS16-NEXT: or $2, $3341; MIPS16-NEXT: $BB2_2:342; MIPS16-NEXT: jrc $ra343;344; MIPS64R2N32-LABEL: pr125954:345; MIPS64R2N32: # %bb.0:346; MIPS64R2N32-NEXT: sll $1, $4, 0347; MIPS64R2N32-NEXT: addiu $2, $zero, -1348; MIPS64R2N32-NEXT: move $3, $1349; MIPS64R2N32-NEXT: ins $3, $2, 8, 24350; MIPS64R2N32-NEXT: andi $2, $1, 255351; MIPS64R2N32-NEXT: sll $1, $5, 0352; MIPS64R2N32-NEXT: andi $1, $1, 1353; MIPS64R2N32-NEXT: jr $ra354; MIPS64R2N32-NEXT: movn $2, $3, $1355 %and = and i32 %arg, 255356 %or = or i32 %and, -256357 %sel = select i1 %c, i32 %or, i32 %and358 ret i32 %sel359}360