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1; RUN: llc -mtriple=mips -mcpu=mips32 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP2; RUN: llc -mtriple=mips -mcpu=mips32r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP3; RUN: llc -mtriple=mips -mcpu=mips32r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP4; RUN: llc -mtriple=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP5; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP6; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP7 8; RUN: llc -mtriple=mips -mcpu=mips32 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK9; RUN: llc -mtriple=mips -mcpu=mips32r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK10; RUN: llc -mtriple=mips -mcpu=mips32r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK11; RUN: llc -mtriple=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK12; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK13; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK14 15; FileCheck Prefixes:16; ALL - All targets17; ACC32 - Accumulator based multiply/divide on 32-bit targets18; ACC64 - Same as ACC32 but only for 64-bit targets19; GPR32 - GPR based multiply/divide on 32-bit targets20; GPR64 - Same as GPR32 but only for 64-bit targets21; ACC32-TRAP - Same as TRAP and ACC32 combined22; ACC64-TRAP - Same as TRAP and ACC64 combined23; GPR32-TRAP - Same as TRAP and GPR32 combined24; GPR64-TRAP - Same as TRAP and GPR64 combined25; NOCHECK - Division by zero will not be detected26 27@g0 = common global i32 0, align 428@g1 = common global i32 0, align 429 30define i32 @sdiv1(i32 signext %a0, i32 signext %a1) nounwind readnone {31entry:32; ALL-LABEL: sdiv1:33 34; ACC32: div $zero, $4, $535; ACC32-TRAP: teq $5, $zero, 736 37; ACC64: div $zero, $4, $538; ACC64-TRAP: teq $5, $zero, 739 40; GPR32: div $2, $4, $541; GPR32-TRAP: teq $5, $zero, 742 43; GPR64: div $2, $4, $544; GPR64-TRAP: teq $5, $zero, 745 46; NOCHECK-NOT: teq47 48; ACC32: mflo $249; ACC64: mflo $250 51; ALL: .end sdiv152 53 %div = sdiv i32 %a0, %a154 ret i32 %div55}56 57define i32 @srem1(i32 signext %a0, i32 signext %a1) nounwind readnone {58entry:59; ALL-LABEL: srem1:60 61; ACC32: div $zero, $4, $562; ACC32-TRAP: teq $5, $zero, 763 64; ACC64: div $zero, $4, $565; ACC64-TRAP: teq $5, $zero, 766 67; GPR32: mod $2, $4, $568; GPR32-TRAP: teq $5, $zero, 769 70; GPR64: mod $2, $4, $571; GPR64-TRAP: teq $5, $zero, 772 73; NOCHECK-NOT: teq74 75; ACC32: mfhi $276; ACC64: mfhi $277 78; ALL: .end srem179 80 %rem = srem i32 %a0, %a181 ret i32 %rem82}83 84define i32 @udiv1(i32 signext %a0, i32 signext %a1) nounwind readnone {85entry:86; ALL-LABEL: udiv1:87 88; ACC32: divu $zero, $4, $589; ACC32-TRAP: teq $5, $zero, 790 91; ACC64: divu $zero, $4, $592; ACC64-TRAP: teq $5, $zero, 793 94; GPR32: divu $2, $4, $595; GPR32-TRAP: teq $5, $zero, 796 97; GPR64: divu $2, $4, $598; GPR64-TRAP: teq $5, $zero, 799 100; NOCHECK-NOT: teq101 102; ACC32: mflo $2103; ACC64: mflo $2104 105; ALL: .end udiv1106 %div = udiv i32 %a0, %a1107 ret i32 %div108}109 110define i32 @urem1(i32 signext %a0, i32 signext %a1) nounwind readnone {111entry:112; ALL-LABEL: urem1:113 114; ACC32: divu $zero, $4, $5115; ACC32-TRAP: teq $5, $zero, 7116 117; ACC64: divu $zero, $4, $5118; ACC64-TRAP: teq $5, $zero, 7119 120; GPR32: modu $2, $4, $5121; GPR32-TRAP: teq $5, $zero, 7122 123; GPR64: modu $2, $4, $5124; GPR64-TRAP: teq $5, $zero, 7125 126; NOCHECK-NOT: teq127 128; ACC32: mfhi $2129; ACC64: mfhi $2130 131; ALL: .end urem1132 133 %rem = urem i32 %a0, %a1134 ret i32 %rem135}136 137define i32 @sdivrem1(i32 signext %a0, i32 signext %a1, ptr nocapture %r) nounwind {138entry:139; ALL-LABEL: sdivrem1:140 141; ACC32: div $zero, $4, $5142; ACC32-TRAP: teq $5, $zero, 7143; NOCHECK-NOT: teq144; ACC32: mflo $2145; ACC32: mfhi $[[R0:[0-9]+]]146; ACC32: sw $[[R0]], 0(${{[0-9]+}})147 148; ACC64: div $zero, $4, $5149; ACC64-TRAP: teq $5, $zero, 7150; NOCHECK-NOT: teq151; ACC64: mflo $2152; ACC64: mfhi $[[R0:[0-9]+]]153; ACC64: sw $[[R0]], 0(${{[0-9]+}})154 155; GPR32-DAG: mod $[[R0:[0-9]+]], $4, $5156; GPR32-TRAP: teq $5, $zero, 7157; NOCHECK-NOT: teq158; GPR32: sw $[[R0]], 0(${{[0-9]+}})159; GPR32-DAG: div $2, $4, $5160; GPR32-TRAP: teq $5, $zero, 7161 162; GPR64-DAG: mod $[[R0:[0-9]+]], $4, $5163; GPR64-TRAP: teq $5, $zero, 7164; NOCHECK-NOT: teq165; GPR64: sw $[[R0]], 0(${{[0-9]+}})166; GPR64-DAG: div $2, $4, $5167; GPR64-TRAP: teq $5, $zero, 7168; NOCHECK-NOT: teq169 170; ALL: .end sdivrem1171 172 %rem = srem i32 %a0, %a1173 store i32 %rem, ptr %r, align 4174 %div = sdiv i32 %a0, %a1175 ret i32 %div176}177 178define i32 @udivrem1(i32 signext %a0, i32 signext %a1, ptr nocapture %r) nounwind {179entry:180; ALL-LABEL: udivrem1:181 182; ACC32: divu $zero, $4, $5183; ACC32-TRAP: teq $5, $zero, 7184; NOCHECK-NOT: teq185; ACC32: mflo $2186; ACC32: mfhi $[[R0:[0-9]+]]187; ACC32: sw $[[R0]], 0(${{[0-9]+}})188 189; ACC64: divu $zero, $4, $5190; ACC64-TRAP: teq $5, $zero, 7191; NOCHECK-NOT: teq192; ACC64: mflo $2193; ACC64: mfhi $[[R0:[0-9]+]]194; ACC64: sw $[[R0]], 0(${{[0-9]+}})195 196; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5197; GPR32-TRAP: teq $5, $zero, 7198; GPR32: sw $[[R0]], 0(${{[0-9]+}})199; NOCHECK-NOT: teq200; GPR32-DAG: divu $2, $4, $5201; GPR32-TRAP: teq $5, $zero, 7202; NOCHECK-NOT: teq203 204; GPR64-DAG: modu $[[R0:[0-9]+]], $4, $5205; GPR64-TRAP: teq $5, $zero, 7206; NOCHECK-NOT: teq207; GPR64: sw $[[R0]], 0(${{[0-9]+}})208; GPR64-DAG: divu $2, $4, $5209; GPR64-TRAP: teq $5, $zero, 7210; NOCHECK-NOT: teq211 212; ALL: .end udivrem1213 214 %rem = urem i32 %a0, %a1215 store i32 %rem, ptr %r, align 4216 %div = udiv i32 %a0, %a1217 ret i32 %div218}219 220; FIXME: It's not clear what this is supposed to test.221define i32 @killFlags() {222entry:223 %0 = load i32, ptr @g0, align 4224 %1 = load i32, ptr @g1, align 4225 %div = sdiv i32 %0, %1226 ret i32 %div227}228 229define i64 @sdiv2(i64 %a0, i64 %a1) nounwind readnone {230entry:231; ALL-LABEL: sdiv2:232 233; ACC32: lw $25, %call16(__divdi3)(234; ACC32: jalr $25235 236; ACC64: ddiv $zero, $4, $5237; ACC64-TRAP: teq $5, $zero, 7238 239; GPR64: ddiv $2, $4, $5240; GPR64-TRAP: teq $5, $zero, 7241 242; NOCHECK-NOT: teq243 244; ACC64: mflo $2245 246; ALL: .end sdiv2247 248 %div = sdiv i64 %a0, %a1249 ret i64 %div250}251 252define i64 @srem2(i64 %a0, i64 %a1) nounwind readnone {253entry:254; ALL-LABEL: srem2:255 256; ACC32: lw $25, %call16(__moddi3)(257; ACC32: jalr $25258 259; ACC64: div $zero, $4, $5260; ACC64-TRAP: teq $5, $zero, 7261 262; GPR64: dmod $2, $4, $5263; GPR64-TRAP: teq $5, $zero, 7264 265; NOCHECK-NOT: teq266 267; ACC64: mfhi $2268 269; ALL: .end srem2270 271 %rem = srem i64 %a0, %a1272 ret i64 %rem273}274 275define i64 @udiv2(i64 %a0, i64 %a1) nounwind readnone {276entry:277; ALL-LABEL: udiv2:278 279; ACC32: lw $25, %call16(__udivdi3)(280; ACC32: jalr $25281 282; ACC64: divu $zero, $4, $5283; ACC64-TRAP: teq $5, $zero, 7284 285; GPR64: ddivu $2, $4, $5286; GPR64-TRAP: teq $5, $zero, 7287 288; NOCHECK-NOT: teq289 290; ACC64: mflo $2291 292; ALL: .end udiv2293 %div = udiv i64 %a0, %a1294 ret i64 %div295}296 297define i64 @urem2(i64 %a0, i64 %a1) nounwind readnone {298entry:299; ALL-LABEL: urem2:300 301; ACC32: lw $25, %call16(__umoddi3)(302; ACC32: jalr $25303 304; ACC64: divu $zero, $4, $5305; ACC64-TRAP: teq $5, $zero, 7306 307; GPR64: dmodu $2, $4, $5308; GPR64-TRAP: teq $5, $zero, 7309 310; NOCHECK-NOT: teq311 312; ACC64: mfhi $2313 314; ALL: .end urem2315 316 %rem = urem i64 %a0, %a1317 ret i64 %rem318}319 320define i64 @sdivrem2(i64 %a0, i64 %a1, ptr nocapture %r) nounwind {321entry:322; ALL-LABEL: sdivrem2:323 324; sdivrem2 is too complex to effectively check. We can at least check for the325; calls though.326; ACC32: lw $25, %call16(__moddi3)(327; ACC32: jalr $25328; ACC32: lw $25, %call16(__divdi3)(329; ACC32: jalr $25330 331; ACC64: ddiv $zero, $4, $5332; ACC64-TRAP: teq $5, $zero, 7333; NOCHECK-NOT: teq334; ACC64: mflo $2335; ACC64: mfhi $[[R0:[0-9]+]]336; ACC64: sd $[[R0]], 0(${{[0-9]+}})337 338; GPR64-DAG: dmod $[[R0:[0-9]+]], $4, $5339; GPR64-TRAP: teq $5, $zero, 7340; NOCHECK-NOT: teq341; GPR64: sd $[[R0]], 0(${{[0-9]+}})342 343; GPR64-DAG: ddiv $2, $4, $5344; GPR64-TRAP: teq $5, $zero, 7345; NOCHECK-NOT: teq346 347; ALL: .end sdivrem2348 349 %rem = srem i64 %a0, %a1350 store i64 %rem, ptr %r, align 8351 %div = sdiv i64 %a0, %a1352 ret i64 %div353}354 355define i64 @udivrem2(i64 %a0, i64 %a1, ptr nocapture %r) nounwind {356entry:357; ALL-LABEL: udivrem2:358 359; udivrem2 is too complex to effectively check. We can at least check for the360; calls though.361; ACC32: lw $25, %call16(__umoddi3)(362; ACC32: jalr $25363; ACC32: lw $25, %call16(__udivdi3)(364; ACC32: jalr $25365 366; ACC64: ddivu $zero, $4, $5367; ACC64-TRAP: teq $5, $zero, 7368; NOCHECK-NOT: teq369; ACC64: mflo $2370; ACC64: mfhi $[[R0:[0-9]+]]371; ACC64: sd $[[R0]], 0(${{[0-9]+}})372 373; GPR64: dmodu $[[R0:[0-9]+]], $4, $5374; GPR64-TRAP: teq $5, $zero, 7375; NOCHECK-NOT: teq376; GPR64: sd $[[R0]], 0(${{[0-9]+}})377 378; GPR64-DAG: ddivu $2, $4, $5379; GPR64-TRAP: teq $5, $zero, 7380; NOCHECK-NOT: teq381 382; ALL: .end udivrem2383 384 %rem = urem i64 %a0, %a1385 store i64 %rem, ptr %r, align 8386 %div = udiv i64 %a0, %a1387 ret i64 %div388}389