1248 lines · plain
1; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \2; RUN: FileCheck %s3 4define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {5entry:6; CHECK: extr.w7 8 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)9 ret i32 %110}11 12declare i32 @llvm.mips.extr.w(i64, i32) nounwind13 14define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {15entry:16; CHECK: extrv.w17 18 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)19 ret i32 %120}21 22define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind {23entry:24; CHECK: extr_r.w25 26 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)27 ret i32 %128}29 30declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind31 32define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {33entry:34; CHECK: extrv_s.h35 36 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)37 ret i32 %138}39 40declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind41 42define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind {43entry:44; CHECK: extr_rs.w45 46 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)47 ret i32 %148}49 50declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind51 52define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {53entry:54; CHECK: extrv_rs.w55 56 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 %a1)57 ret i32 %158}59 60define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind {61entry:62; CHECK: extr_s.h63 64 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 15)65 ret i32 %166}67 68define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {69entry:70; CHECK: extrv_r.w71 72 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 %a1)73 ret i32 %174}75 76define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {77entry:78; CHECK: extp ${{[0-9]+}}79 80 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 15)81 ret i32 %182}83 84declare i32 @llvm.mips.extp(i64, i32) nounwind85 86define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {87entry:88; CHECK: extpv89 90 %1 = tail call i32 @llvm.mips.extp(i64 %a0, i32 %a1)91 ret i32 %192}93 94define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {95entry:96; CHECK: extpdp ${{[0-9]+}}97 98 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 15)99 ret i32 %1100}101 102declare i32 @llvm.mips.extpdp(i64, i32) nounwind103 104define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {105entry:106; CHECK: extpdpv107 108 %1 = tail call i32 @llvm.mips.extpdp(i64 %a0, i32 %a1)109 ret i32 %1110}111 112define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {113entry:114; CHECK: dpau.h.qbl115 116 %1 = bitcast i32 %a1.coerce to <4 x i8>117 %2 = bitcast i32 %a2.coerce to <4 x i8>118 %3 = tail call i64 @llvm.mips.dpau.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2)119 ret i64 %3120}121 122declare i64 @llvm.mips.dpau.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone123 124define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {125entry:126; CHECK: dpau.h.qbr127 128 %1 = bitcast i32 %a1.coerce to <4 x i8>129 %2 = bitcast i32 %a2.coerce to <4 x i8>130 %3 = tail call i64 @llvm.mips.dpau.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)131 ret i64 %3132}133 134declare i64 @llvm.mips.dpau.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone135 136define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {137entry:138; CHECK: dpsu.h.qbl139 140 %1 = bitcast i32 %a1.coerce to <4 x i8>141 %2 = bitcast i32 %a2.coerce to <4 x i8>142 %3 = tail call i64 @llvm.mips.dpsu.h.qbl(i64 %a0, <4 x i8> %1, <4 x i8> %2)143 ret i64 %3144}145 146declare i64 @llvm.mips.dpsu.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone147 148define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {149entry:150; CHECK: dpsu.h.qbr151 152 %1 = bitcast i32 %a1.coerce to <4 x i8>153 %2 = bitcast i32 %a2.coerce to <4 x i8>154 %3 = tail call i64 @llvm.mips.dpsu.h.qbr(i64 %a0, <4 x i8> %1, <4 x i8> %2)155 ret i64 %3156}157 158declare i64 @llvm.mips.dpsu.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone159 160define i64 @test__builtin_mips_dpaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {161entry:162; CHECK: dpaq_s.w.ph163 164 %1 = bitcast i32 %a1.coerce to <2 x i16>165 %2 = bitcast i32 %a2.coerce to <2 x i16>166 %3 = tail call i64 @llvm.mips.dpaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)167 ret i64 %3168}169 170declare i64 @llvm.mips.dpaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind171 172define i64 @test__builtin_mips_dpaq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {173entry:174; CHECK: dpaq_sa.l.w175 176 %1 = tail call i64 @llvm.mips.dpaq.sa.l.w(i64 %a0, i32 %a1, i32 %a2)177 ret i64 %1178}179 180declare i64 @llvm.mips.dpaq.sa.l.w(i64, i32, i32) nounwind181 182define i64 @test__builtin_mips_dpsq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {183entry:184; CHECK: dpsq_s.w.ph185 186 %1 = bitcast i32 %a1.coerce to <2 x i16>187 %2 = bitcast i32 %a2.coerce to <2 x i16>188 %3 = tail call i64 @llvm.mips.dpsq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)189 ret i64 %3190}191 192declare i64 @llvm.mips.dpsq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind193 194define i64 @test__builtin_mips_dpsq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {195entry:196; CHECK: dpsq_sa.l.w197 198 %1 = tail call i64 @llvm.mips.dpsq.sa.l.w(i64 %a0, i32 %a1, i32 %a2)199 ret i64 %1200}201 202declare i64 @llvm.mips.dpsq.sa.l.w(i64, i32, i32) nounwind203 204define i64 @test__builtin_mips_mulsaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {205entry:206; CHECK: mulsaq_s.w.ph207 208 %1 = bitcast i32 %a1.coerce to <2 x i16>209 %2 = bitcast i32 %a2.coerce to <2 x i16>210 %3 = tail call i64 @llvm.mips.mulsaq.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)211 ret i64 %3212}213 214declare i64 @llvm.mips.mulsaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind215 216define i64 @test__builtin_mips_maq_s_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {217entry:218; CHECK: maq_s.w.phl219 220 %1 = bitcast i32 %a1.coerce to <2 x i16>221 %2 = bitcast i32 %a2.coerce to <2 x i16>222 %3 = tail call i64 @llvm.mips.maq.s.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2)223 ret i64 %3224}225 226declare i64 @llvm.mips.maq.s.w.phl(i64, <2 x i16>, <2 x i16>) nounwind227 228define i64 @test__builtin_mips_maq_s_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {229entry:230; CHECK: maq_s.w.phr231 232 %1 = bitcast i32 %a1.coerce to <2 x i16>233 %2 = bitcast i32 %a2.coerce to <2 x i16>234 %3 = tail call i64 @llvm.mips.maq.s.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2)235 ret i64 %3236}237 238declare i64 @llvm.mips.maq.s.w.phr(i64, <2 x i16>, <2 x i16>) nounwind239 240define i64 @test__builtin_mips_maq_sa_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {241entry:242; CHECK: maq_sa.w.phl243 244 %1 = bitcast i32 %a1.coerce to <2 x i16>245 %2 = bitcast i32 %a2.coerce to <2 x i16>246 %3 = tail call i64 @llvm.mips.maq.sa.w.phl(i64 %a0, <2 x i16> %1, <2 x i16> %2)247 ret i64 %3248}249 250declare i64 @llvm.mips.maq.sa.w.phl(i64, <2 x i16>, <2 x i16>) nounwind251 252define i64 @test__builtin_mips_maq_sa_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {253entry:254; CHECK: maq_sa.w.phr255 256 %1 = bitcast i32 %a1.coerce to <2 x i16>257 %2 = bitcast i32 %a2.coerce to <2 x i16>258 %3 = tail call i64 @llvm.mips.maq.sa.w.phr(i64 %a0, <2 x i16> %1, <2 x i16> %2)259 ret i64 %3260}261 262declare i64 @llvm.mips.maq.sa.w.phr(i64, <2 x i16>, <2 x i16>) nounwind263 264define i64 @test__builtin_mips_shilo1(i32 %i0, i32, i64 %a0) nounwind readnone {265entry:266; CHECK: shilo $ac{{[0-9]}}267 268 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 0)269 ret i64 %1270}271 272declare i64 @llvm.mips.shilo(i64, i32) nounwind readnone273 274define i64 @test__builtin_mips_shilo2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind readnone {275entry:276; CHECK: shilov277 278 %1 = tail call i64 @llvm.mips.shilo(i64 %a0, i32 %a1)279 ret i64 %1280}281 282define i64 @test__builtin_mips_mthlip1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {283entry:284; CHECK: mthlip ${{[0-9]+}}285 286 %1 = tail call i64 @llvm.mips.mthlip(i64 %a0, i32 %a1)287 ret i64 %1288}289 290declare i64 @llvm.mips.mthlip(i64, i32) nounwind291 292define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly {293entry:294; CHECK: bposge32 $BB{{[0-9]+}}295 296 %0 = tail call i32 @llvm.mips.bposge32()297 ret i32 %0298}299 300declare i32 @llvm.mips.bposge32() nounwind readonly301 302define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {303entry:304; CHECK: madd $ac{{[0-9]}}305 306 %1 = tail call i64 @llvm.mips.madd(i64 %a0, i32 %a1, i32 %a2)307 ret i64 %1308}309 310declare i64 @llvm.mips.madd(i64, i32, i32) nounwind readnone311 312define i64 @test__builtin_mips_maddu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {313entry:314; CHECK: maddu $ac{{[0-9]}}315 316 %1 = tail call i64 @llvm.mips.maddu(i64 %a0, i32 %a1, i32 %a2)317 ret i64 %1318}319 320declare i64 @llvm.mips.maddu(i64, i32, i32) nounwind readnone321 322define i64 @test__builtin_mips_msub1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {323entry:324; CHECK: msub $ac{{[0-9]}}325 326 %1 = tail call i64 @llvm.mips.msub(i64 %a0, i32 %a1, i32 %a2)327 ret i64 %1328}329 330declare i64 @llvm.mips.msub(i64, i32, i32) nounwind readnone331 332define i64 @test__builtin_mips_msubu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {333entry:334; CHECK: msubu $ac{{[0-9]}}335 336 %1 = tail call i64 @llvm.mips.msubu(i64 %a0, i32 %a1, i32 %a2)337 ret i64 %1338}339 340declare i64 @llvm.mips.msubu(i64, i32, i32) nounwind readnone341 342define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {343entry:344; CHECK: mult $ac{{[0-9]}}345 346 %0 = tail call i64 @llvm.mips.mult(i32 %a0, i32 %a1)347 ret i64 %0348}349 350declare i64 @llvm.mips.mult(i32, i32) nounwind readnone351 352define i64 @test__builtin_mips_multu1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {353entry:354; CHECK: multu $ac{{[0-9]}}355 356 %0 = tail call i64 @llvm.mips.multu(i32 %a0, i32 %a1)357 ret i64 %0358}359 360declare i64 @llvm.mips.multu(i32, i32) nounwind readnone361 362define { i32 } @test__builtin_mips_addq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {363entry:364; CHECK: addq.ph365 366 %0 = bitcast i32 %a0.coerce to <2 x i16>367 %1 = bitcast i32 %a1.coerce to <2 x i16>368 %2 = tail call <2 x i16> @llvm.mips.addq.ph(<2 x i16> %0, <2 x i16> %1)369 %3 = bitcast <2 x i16> %2 to i32370 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0371 ret { i32 } %.fca.0.insert372}373 374declare <2 x i16> @llvm.mips.addq.ph(<2 x i16>, <2 x i16>) nounwind375 376define { i32 } @test__builtin_mips_addq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {377entry:378; CHECK: addq_s.ph379 380 %0 = bitcast i32 %a0.coerce to <2 x i16>381 %1 = bitcast i32 %a1.coerce to <2 x i16>382 %2 = tail call <2 x i16> @llvm.mips.addq.s.ph(<2 x i16> %0, <2 x i16> %1)383 %3 = bitcast <2 x i16> %2 to i32384 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0385 ret { i32 } %.fca.0.insert386}387 388declare <2 x i16> @llvm.mips.addq.s.ph(<2 x i16>, <2 x i16>) nounwind389 390define i32 @test__builtin_mips_addq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {391entry:392; CHECK: addq_s.w393 394 %0 = tail call i32 @llvm.mips.addq.s.w(i32 %a0, i32 %a1)395 ret i32 %0396}397 398declare i32 @llvm.mips.addq.s.w(i32, i32) nounwind399 400define { i32 } @test__builtin_mips_addu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {401entry:402; CHECK: addu.qb403 404 %0 = bitcast i32 %a0.coerce to <4 x i8>405 %1 = bitcast i32 %a1.coerce to <4 x i8>406 %2 = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %0, <4 x i8> %1)407 %3 = bitcast <4 x i8> %2 to i32408 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0409 ret { i32 } %.fca.0.insert410}411 412declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind413 414define { i32 } @test__builtin_mips_addu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {415entry:416; CHECK: addu_s.qb417 418 %0 = bitcast i32 %a0.coerce to <4 x i8>419 %1 = bitcast i32 %a1.coerce to <4 x i8>420 %2 = tail call <4 x i8> @llvm.mips.addu.s.qb(<4 x i8> %0, <4 x i8> %1)421 %3 = bitcast <4 x i8> %2 to i32422 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0423 ret { i32 } %.fca.0.insert424}425 426declare <4 x i8> @llvm.mips.addu.s.qb(<4 x i8>, <4 x i8>) nounwind427 428define { i32 } @test__builtin_mips_subq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {429entry:430; CHECK: subq.ph431 432 %0 = bitcast i32 %a0.coerce to <2 x i16>433 %1 = bitcast i32 %a1.coerce to <2 x i16>434 %2 = tail call <2 x i16> @llvm.mips.subq.ph(<2 x i16> %0, <2 x i16> %1)435 %3 = bitcast <2 x i16> %2 to i32436 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0437 ret { i32 } %.fca.0.insert438}439 440declare <2 x i16> @llvm.mips.subq.ph(<2 x i16>, <2 x i16>) nounwind441 442define { i32 } @test__builtin_mips_subq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {443entry:444; CHECK: subq_s.ph445 446 %0 = bitcast i32 %a0.coerce to <2 x i16>447 %1 = bitcast i32 %a1.coerce to <2 x i16>448 %2 = tail call <2 x i16> @llvm.mips.subq.s.ph(<2 x i16> %0, <2 x i16> %1)449 %3 = bitcast <2 x i16> %2 to i32450 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0451 ret { i32 } %.fca.0.insert452}453 454declare <2 x i16> @llvm.mips.subq.s.ph(<2 x i16>, <2 x i16>) nounwind455 456define i32 @test__builtin_mips_subq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {457entry:458; CHECK: subq_s.w459 460 %0 = tail call i32 @llvm.mips.subq.s.w(i32 %a0, i32 %a1)461 ret i32 %0462}463 464declare i32 @llvm.mips.subq.s.w(i32, i32) nounwind465 466define { i32 } @test__builtin_mips_subu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {467entry:468; CHECK: subu.qb469 470 %0 = bitcast i32 %a0.coerce to <4 x i8>471 %1 = bitcast i32 %a1.coerce to <4 x i8>472 %2 = tail call <4 x i8> @llvm.mips.subu.qb(<4 x i8> %0, <4 x i8> %1)473 %3 = bitcast <4 x i8> %2 to i32474 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0475 ret { i32 } %.fca.0.insert476}477 478declare <4 x i8> @llvm.mips.subu.qb(<4 x i8>, <4 x i8>) nounwind479 480define { i32 } @test__builtin_mips_subu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {481entry:482; CHECK: subu_s.qb483 484 %0 = bitcast i32 %a0.coerce to <4 x i8>485 %1 = bitcast i32 %a1.coerce to <4 x i8>486 %2 = tail call <4 x i8> @llvm.mips.subu.s.qb(<4 x i8> %0, <4 x i8> %1)487 %3 = bitcast <4 x i8> %2 to i32488 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0489 ret { i32 } %.fca.0.insert490}491 492declare <4 x i8> @llvm.mips.subu.s.qb(<4 x i8>, <4 x i8>) nounwind493 494define i32 @test__builtin_mips_addsc1(i32 %i0, i32 %a0, i32 %a1) nounwind {495entry:496; CHECK: addsc ${{[0-9]+}}497 498 %0 = tail call i32 @llvm.mips.addsc(i32 %a0, i32 %a1)499 ret i32 %0500}501 502declare i32 @llvm.mips.addsc(i32, i32) nounwind503 504define i32 @test__builtin_mips_addwc1(i32 %i0, i32 %a0, i32 %a1) nounwind {505entry:506; CHECK: addwc ${{[0-9]+}}507 508 %0 = tail call i32 @llvm.mips.addwc(i32 %a0, i32 %a1)509 ret i32 %0510}511 512declare i32 @llvm.mips.addwc(i32, i32) nounwind513 514define i32 @test__builtin_mips_modsub1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {515entry:516; CHECK: modsub ${{[0-9]+}}517 518 %0 = tail call i32 @llvm.mips.modsub(i32 %a0, i32 %a1)519 ret i32 %0520}521 522declare i32 @llvm.mips.modsub(i32, i32) nounwind readnone523 524define i32 @test__builtin_mips_raddu_w_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {525entry:526; CHECK: raddu.w.qb527 528 %0 = bitcast i32 %a0.coerce to <4 x i8>529 %1 = tail call i32 @llvm.mips.raddu.w.qb(<4 x i8> %0)530 ret i32 %1531}532 533declare i32 @llvm.mips.raddu.w.qb(<4 x i8>) nounwind readnone534 535define { i32 } @test__builtin_mips_muleu_s_ph_qbl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {536entry:537; CHECK: muleu_s.ph.qbl538 539 %0 = bitcast i32 %a0.coerce to <4 x i8>540 %1 = bitcast i32 %a1.coerce to <2 x i16>541 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8> %0, <2 x i16> %1)542 %3 = bitcast <2 x i16> %2 to i32543 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0544 ret { i32 } %.fca.0.insert545}546 547declare <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8>, <2 x i16>) nounwind548 549define { i32 } @test__builtin_mips_muleu_s_ph_qbr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {550entry:551; CHECK: muleu_s.ph.qbr552 553 %0 = bitcast i32 %a0.coerce to <4 x i8>554 %1 = bitcast i32 %a1.coerce to <2 x i16>555 %2 = tail call <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8> %0, <2 x i16> %1)556 %3 = bitcast <2 x i16> %2 to i32557 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0558 ret { i32 } %.fca.0.insert559}560 561declare <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8>, <2 x i16>) nounwind562 563define { i32 } @test__builtin_mips_mulq_rs_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {564entry:565; CHECK: mulq_rs.ph566 567 %0 = bitcast i32 %a0.coerce to <2 x i16>568 %1 = bitcast i32 %a1.coerce to <2 x i16>569 %2 = tail call <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16> %0, <2 x i16> %1)570 %3 = bitcast <2 x i16> %2 to i32571 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0572 ret { i32 } %.fca.0.insert573}574 575declare <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16>, <2 x i16>) nounwind576 577define i32 @test__builtin_mips_muleq_s_w_phl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {578entry:579; CHECK: muleq_s.w.phl580 581 %0 = bitcast i32 %a0.coerce to <2 x i16>582 %1 = bitcast i32 %a1.coerce to <2 x i16>583 %2 = tail call i32 @llvm.mips.muleq.s.w.phl(<2 x i16> %0, <2 x i16> %1)584 ret i32 %2585}586 587declare i32 @llvm.mips.muleq.s.w.phl(<2 x i16>, <2 x i16>) nounwind588 589define i32 @test__builtin_mips_muleq_s_w_phr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {590entry:591; CHECK: muleq_s.w.phr592 593 %0 = bitcast i32 %a0.coerce to <2 x i16>594 %1 = bitcast i32 %a1.coerce to <2 x i16>595 %2 = tail call i32 @llvm.mips.muleq.s.w.phr(<2 x i16> %0, <2 x i16> %1)596 ret i32 %2597}598 599declare i32 @llvm.mips.muleq.s.w.phr(<2 x i16>, <2 x i16>) nounwind600 601define { i32 } @test__builtin_mips_precrq_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {602entry:603; CHECK: precrq.qb.ph604 605 %0 = bitcast i32 %a0.coerce to <2 x i16>606 %1 = bitcast i32 %a1.coerce to <2 x i16>607 %2 = tail call <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16> %0, <2 x i16> %1)608 %3 = bitcast <4 x i8> %2 to i32609 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0610 ret { i32 } %.fca.0.insert611}612 613declare <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16>, <2 x i16>) nounwind readnone614 615define { i32 } @test__builtin_mips_precrq_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {616entry:617; CHECK: precrq.ph.w618 619 %0 = tail call <2 x i16> @llvm.mips.precrq.ph.w(i32 %a0, i32 %a1)620 %1 = bitcast <2 x i16> %0 to i32621 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0622 ret { i32 } %.fca.0.insert623}624 625declare <2 x i16> @llvm.mips.precrq.ph.w(i32, i32) nounwind readnone626 627define { i32 } @test__builtin_mips_precrq_rs_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {628entry:629; CHECK: precrq_rs.ph.w630 631 %0 = tail call <2 x i16> @llvm.mips.precrq.rs.ph.w(i32 %a0, i32 %a1)632 %1 = bitcast <2 x i16> %0 to i32633 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0634 ret { i32 } %.fca.0.insert635}636 637declare <2 x i16> @llvm.mips.precrq.rs.ph.w(i32, i32) nounwind638 639define { i32 } @test__builtin_mips_precrqu_s_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {640entry:641; CHECK: precrqu_s.qb.ph642 643 %0 = bitcast i32 %a0.coerce to <2 x i16>644 %1 = bitcast i32 %a1.coerce to <2 x i16>645 %2 = tail call <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16> %0, <2 x i16> %1)646 %3 = bitcast <4 x i8> %2 to i32647 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0648 ret { i32 } %.fca.0.insert649}650 651declare <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16>, <2 x i16>) nounwind652 653 654define i32 @test__builtin_mips_cmpu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {655entry:656; CHECK: cmpu.eq.qb657 658 %0 = bitcast i32 %a0.coerce to <4 x i8>659 %1 = bitcast i32 %a1.coerce to <4 x i8>660 tail call void @llvm.mips.cmpu.eq.qb(<4 x i8> %0, <4 x i8> %1)661 %2 = tail call i32 @llvm.mips.rddsp(i32 31)662 ret i32 %2663}664 665declare void @llvm.mips.cmpu.eq.qb(<4 x i8>, <4 x i8>) nounwind666 667declare i32 @llvm.mips.rddsp(i32) nounwind readonly668 669define i32 @test__builtin_mips_cmpu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {670entry:671; CHECK: cmpu.lt.qb672 673 %0 = bitcast i32 %a0.coerce to <4 x i8>674 %1 = bitcast i32 %a1.coerce to <4 x i8>675 tail call void @llvm.mips.cmpu.lt.qb(<4 x i8> %0, <4 x i8> %1)676 %2 = tail call i32 @llvm.mips.rddsp(i32 31)677 ret i32 %2678}679 680declare void @llvm.mips.cmpu.lt.qb(<4 x i8>, <4 x i8>) nounwind681 682define i32 @test__builtin_mips_cmpu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {683entry:684; CHECK: cmpu.le.qb685 686 %0 = bitcast i32 %a0.coerce to <4 x i8>687 %1 = bitcast i32 %a1.coerce to <4 x i8>688 tail call void @llvm.mips.cmpu.le.qb(<4 x i8> %0, <4 x i8> %1)689 %2 = tail call i32 @llvm.mips.rddsp(i32 31)690 ret i32 %2691}692 693declare void @llvm.mips.cmpu.le.qb(<4 x i8>, <4 x i8>) nounwind694 695define i32 @test__builtin_mips_cmpgu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {696entry:697; CHECK: cmpgu.eq.qb698 699 %0 = bitcast i32 %a0.coerce to <4 x i8>700 %1 = bitcast i32 %a1.coerce to <4 x i8>701 %2 = tail call i32 @llvm.mips.cmpgu.eq.qb(<4 x i8> %0, <4 x i8> %1)702 ret i32 %2703}704 705declare i32 @llvm.mips.cmpgu.eq.qb(<4 x i8>, <4 x i8>) nounwind706 707define i32 @test__builtin_mips_cmpgu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {708entry:709; CHECK: cmpgu.lt.qb710 711 %0 = bitcast i32 %a0.coerce to <4 x i8>712 %1 = bitcast i32 %a1.coerce to <4 x i8>713 %2 = tail call i32 @llvm.mips.cmpgu.lt.qb(<4 x i8> %0, <4 x i8> %1)714 ret i32 %2715}716 717declare i32 @llvm.mips.cmpgu.lt.qb(<4 x i8>, <4 x i8>) nounwind718 719define i32 @test__builtin_mips_cmpgu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {720entry:721; CHECK: cmpgu.le.qb722 723 %0 = bitcast i32 %a0.coerce to <4 x i8>724 %1 = bitcast i32 %a1.coerce to <4 x i8>725 %2 = tail call i32 @llvm.mips.cmpgu.le.qb(<4 x i8> %0, <4 x i8> %1)726 ret i32 %2727}728 729declare i32 @llvm.mips.cmpgu.le.qb(<4 x i8>, <4 x i8>) nounwind730 731define i32 @test__builtin_mips_cmp_eq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {732entry:733; CHECK: cmp.eq.ph734 735 %0 = bitcast i32 %a0.coerce to <2 x i16>736 %1 = bitcast i32 %a1.coerce to <2 x i16>737 tail call void @llvm.mips.cmp.eq.ph(<2 x i16> %0, <2 x i16> %1)738 %2 = tail call i32 @llvm.mips.rddsp(i32 31)739 ret i32 %2740}741 742declare void @llvm.mips.cmp.eq.ph(<2 x i16>, <2 x i16>) nounwind743 744define i32 @test__builtin_mips_cmp_lt_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {745entry:746; CHECK: cmp.lt.ph747 748 %0 = bitcast i32 %a0.coerce to <2 x i16>749 %1 = bitcast i32 %a1.coerce to <2 x i16>750 tail call void @llvm.mips.cmp.lt.ph(<2 x i16> %0, <2 x i16> %1)751 %2 = tail call i32 @llvm.mips.rddsp(i32 31)752 ret i32 %2753}754 755declare void @llvm.mips.cmp.lt.ph(<2 x i16>, <2 x i16>) nounwind756 757define i32 @test__builtin_mips_cmp_le_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {758entry:759; CHECK: cmp.le.ph760 761 %0 = bitcast i32 %a0.coerce to <2 x i16>762 %1 = bitcast i32 %a1.coerce to <2 x i16>763 tail call void @llvm.mips.cmp.le.ph(<2 x i16> %0, <2 x i16> %1)764 %2 = tail call i32 @llvm.mips.rddsp(i32 31)765 ret i32 %2766}767 768declare void @llvm.mips.cmp.le.ph(<2 x i16>, <2 x i16>) nounwind769 770define { i32 } @test__builtin_mips_pick_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly {771entry:772; CHECK: pick.qb773 774 %0 = bitcast i32 %a0.coerce to <4 x i8>775 %1 = bitcast i32 %a1.coerce to <4 x i8>776 tail call void @llvm.mips.wrdsp(i32 %i0, i32 16)777 %2 = tail call <4 x i8> @llvm.mips.pick.qb(<4 x i8> %0, <4 x i8> %1)778 %3 = bitcast <4 x i8> %2 to i32779 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0780 ret { i32 } %.fca.0.insert781}782 783declare <4 x i8> @llvm.mips.pick.qb(<4 x i8>, <4 x i8>) nounwind readonly784 785define { i32 } @test__builtin_mips_pick_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly {786entry:787; CHECK: pick.ph788 789 %0 = bitcast i32 %a0.coerce to <2 x i16>790 %1 = bitcast i32 %a1.coerce to <2 x i16>791 tail call void @llvm.mips.wrdsp(i32 %i0, i32 16)792 %2 = tail call <2 x i16> @llvm.mips.pick.ph(<2 x i16> %0, <2 x i16> %1)793 %3 = bitcast <2 x i16> %2 to i32794 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0795 ret { i32 } %.fca.0.insert796}797 798declare <2 x i16> @llvm.mips.pick.ph(<2 x i16>, <2 x i16>) nounwind readonly799 800define { i32 } @test__builtin_mips_packrl_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {801entry:802; CHECK: packrl.ph803 804 %0 = bitcast i32 %a0.coerce to <2 x i16>805 %1 = bitcast i32 %a1.coerce to <2 x i16>806 %2 = tail call <2 x i16> @llvm.mips.packrl.ph(<2 x i16> %0, <2 x i16> %1)807 %3 = bitcast <2 x i16> %2 to i32808 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0809 ret { i32 } %.fca.0.insert810}811 812declare <2 x i16> @llvm.mips.packrl.ph(<2 x i16>, <2 x i16>) nounwind readnone813 814define { i32 } @test__builtin_mips_shll_qb1(i32 %i0, i32 %a0.coerce) nounwind {815entry:816; CHECK: shll.qb817 818 %0 = bitcast i32 %a0.coerce to <4 x i8>819 %1 = tail call <4 x i8> @llvm.mips.shll.qb(<4 x i8> %0, i32 3)820 %2 = bitcast <4 x i8> %1 to i32821 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0822 ret { i32 } %.fca.0.insert823}824 825declare <4 x i8> @llvm.mips.shll.qb(<4 x i8>, i32) nounwind826 827define { i32 } @test__builtin_mips_shll_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {828entry:829; CHECK: shllv.qb830 831 %0 = bitcast i32 %a0.coerce to <4 x i8>832 %1 = tail call <4 x i8> @llvm.mips.shll.qb(<4 x i8> %0, i32 %a1)833 %2 = bitcast <4 x i8> %1 to i32834 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0835 ret { i32 } %.fca.0.insert836}837 838define { i32 } @test__builtin_mips_shll_ph1(i32 %i0, i32 %a0.coerce) nounwind {839entry:840; CHECK: shll.ph841 842 %0 = bitcast i32 %a0.coerce to <2 x i16>843 %1 = tail call <2 x i16> @llvm.mips.shll.ph(<2 x i16> %0, i32 7)844 %2 = bitcast <2 x i16> %1 to i32845 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0846 ret { i32 } %.fca.0.insert847}848 849declare <2 x i16> @llvm.mips.shll.ph(<2 x i16>, i32) nounwind850 851define { i32 } @test__builtin_mips_shll_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {852entry:853; CHECK: shllv.ph854 855 %0 = bitcast i32 %a0.coerce to <2 x i16>856 %1 = tail call <2 x i16> @llvm.mips.shll.ph(<2 x i16> %0, i32 %a1)857 %2 = bitcast <2 x i16> %1 to i32858 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0859 ret { i32 } %.fca.0.insert860}861 862define { i32 } @test__builtin_mips_shll_s_ph1(i32 %i0, i32 %a0.coerce) nounwind {863entry:864; CHECK: shll_s.ph865 866 %0 = bitcast i32 %a0.coerce to <2 x i16>867 %1 = tail call <2 x i16> @llvm.mips.shll.s.ph(<2 x i16> %0, i32 7)868 %2 = bitcast <2 x i16> %1 to i32869 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0870 ret { i32 } %.fca.0.insert871}872 873declare <2 x i16> @llvm.mips.shll.s.ph(<2 x i16>, i32) nounwind874 875define { i32 } @test__builtin_mips_shll_s_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {876entry:877; CHECK: shllv_s.ph878 879 %0 = bitcast i32 %a0.coerce to <2 x i16>880 %1 = tail call <2 x i16> @llvm.mips.shll.s.ph(<2 x i16> %0, i32 %a1)881 %2 = bitcast <2 x i16> %1 to i32882 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0883 ret { i32 } %.fca.0.insert884}885 886define i32 @test__builtin_mips_shll_s_w1(i32 %i0, i32 %a0) nounwind {887entry:888; CHECK: shll_s.w889 890 %0 = tail call i32 @llvm.mips.shll.s.w(i32 %a0, i32 15)891 ret i32 %0892}893 894declare i32 @llvm.mips.shll.s.w(i32, i32) nounwind895 896define i32 @test__builtin_mips_shll_s_w2(i32 %i0, i32 %a0, i32 %a1) nounwind {897entry:898; CHECK: shllv_s.w899 900 %0 = tail call i32 @llvm.mips.shll.s.w(i32 %a0, i32 %a1)901 ret i32 %0902}903 904define { i32 } @test__builtin_mips_shrl_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {905entry:906; CHECK: shrl.qb907 908 %0 = bitcast i32 %a0.coerce to <4 x i8>909 %1 = tail call <4 x i8> @llvm.mips.shrl.qb(<4 x i8> %0, i32 3)910 %2 = bitcast <4 x i8> %1 to i32911 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0912 ret { i32 } %.fca.0.insert913}914 915declare <4 x i8> @llvm.mips.shrl.qb(<4 x i8>, i32) nounwind readnone916 917define { i32 } @test__builtin_mips_shrl_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {918entry:919; CHECK: shrlv.qb920 921 %0 = bitcast i32 %a0.coerce to <4 x i8>922 %1 = tail call <4 x i8> @llvm.mips.shrl.qb(<4 x i8> %0, i32 %a1)923 %2 = bitcast <4 x i8> %1 to i32924 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0925 ret { i32 } %.fca.0.insert926}927 928define { i32 } @test__builtin_mips_shra_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone {929entry:930; CHECK: shra.ph931 932 %0 = bitcast i32 %a0.coerce to <2 x i16>933 %1 = tail call <2 x i16> @llvm.mips.shra.ph(<2 x i16> %0, i32 7)934 %2 = bitcast <2 x i16> %1 to i32935 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0936 ret { i32 } %.fca.0.insert937}938 939declare <2 x i16> @llvm.mips.shra.ph(<2 x i16>, i32) nounwind readnone940 941define { i32 } @test__builtin_mips_shra_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {942entry:943; CHECK: shrav.ph944 945 %0 = bitcast i32 %a0.coerce to <2 x i16>946 %1 = tail call <2 x i16> @llvm.mips.shra.ph(<2 x i16> %0, i32 %a1)947 %2 = bitcast <2 x i16> %1 to i32948 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0949 ret { i32 } %.fca.0.insert950}951 952define { i32 } @test__builtin_mips_shra_r_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone {953entry:954; CHECK: shra_r.ph955 956 %0 = bitcast i32 %a0.coerce to <2 x i16>957 %1 = tail call <2 x i16> @llvm.mips.shra.r.ph(<2 x i16> %0, i32 7)958 %2 = bitcast <2 x i16> %1 to i32959 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0960 ret { i32 } %.fca.0.insert961}962 963declare <2 x i16> @llvm.mips.shra.r.ph(<2 x i16>, i32) nounwind readnone964 965define { i32 } @test__builtin_mips_shra_r_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {966entry:967; CHECK: shrav_r.ph968 969 %0 = bitcast i32 %a0.coerce to <2 x i16>970 %1 = tail call <2 x i16> @llvm.mips.shra.r.ph(<2 x i16> %0, i32 %a1)971 %2 = bitcast <2 x i16> %1 to i32972 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0973 ret { i32 } %.fca.0.insert974}975 976define i32 @test__builtin_mips_shra_r_w1(i32 %i0, i32 %a0) nounwind readnone {977entry:978; CHECK: shra_r.w979 980 %0 = tail call i32 @llvm.mips.shra.r.w(i32 %a0, i32 15)981 ret i32 %0982}983 984declare i32 @llvm.mips.shra.r.w(i32, i32) nounwind readnone985 986define i32 @test__builtin_mips_shra_r_w2(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {987entry:988; CHECK: shrav_r.w989 990 %0 = tail call i32 @llvm.mips.shra.r.w(i32 %a0, i32 %a1)991 ret i32 %0992}993 994define { i32 } @test__builtin_mips_absq_s_ph1(i32 %i0, i32 %a0.coerce) nounwind {995entry:996; CHECK: absq_s.ph997 998 %0 = bitcast i32 %a0.coerce to <2 x i16>999 %1 = tail call <2 x i16> @llvm.mips.absq.s.ph(<2 x i16> %0)1000 %2 = bitcast <2 x i16> %1 to i321001 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01002 ret { i32 } %.fca.0.insert1003}1004 1005declare <2 x i16> @llvm.mips.absq.s.ph(<2 x i16>) nounwind1006 1007define i32 @test__builtin_mips_absq_s_w1(i32 %i0, i32 %a0) nounwind {1008entry:1009; CHECK: absq_s.w1010 1011 %0 = tail call i32 @llvm.mips.absq.s.w(i32 %a0)1012 ret i32 %01013}1014 1015declare i32 @llvm.mips.absq.s.w(i32) nounwind1016 1017define i32 @test__builtin_mips_preceq_w_phl1(i32 %i0, i32 %a0.coerce) nounwind readnone {1018entry:1019; CHECK: preceq.w.phl1020 1021 %0 = bitcast i32 %a0.coerce to <2 x i16>1022 %1 = tail call i32 @llvm.mips.preceq.w.phl(<2 x i16> %0)1023 ret i32 %11024}1025 1026declare i32 @llvm.mips.preceq.w.phl(<2 x i16>) nounwind readnone1027 1028define i32 @test__builtin_mips_preceq_w_phr1(i32 %i0, i32 %a0.coerce) nounwind readnone {1029entry:1030; CHECK: preceq.w.phr1031 1032 %0 = bitcast i32 %a0.coerce to <2 x i16>1033 %1 = tail call i32 @llvm.mips.preceq.w.phr(<2 x i16> %0)1034 ret i32 %11035}1036 1037declare i32 @llvm.mips.preceq.w.phr(<2 x i16>) nounwind readnone1038 1039define { i32 } @test__builtin_mips_precequ_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone {1040entry:1041; CHECK: precequ.ph.qbl1042 1043 %0 = bitcast i32 %a0.coerce to <4 x i8>1044 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8> %0)1045 %2 = bitcast <2 x i16> %1 to i321046 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01047 ret { i32 } %.fca.0.insert1048}1049 1050declare <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8>) nounwind readnone1051 1052define { i32 } @test__builtin_mips_precequ_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone {1053entry:1054; CHECK: precequ.ph.qbr1055 1056 %0 = bitcast i32 %a0.coerce to <4 x i8>1057 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8> %0)1058 %2 = bitcast <2 x i16> %1 to i321059 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01060 ret { i32 } %.fca.0.insert1061}1062 1063declare <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8>) nounwind readnone1064 1065define { i32 } @test__builtin_mips_precequ_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone {1066entry:1067; CHECK: precequ.ph.qbla1068 1069 %0 = bitcast i32 %a0.coerce to <4 x i8>1070 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8> %0)1071 %2 = bitcast <2 x i16> %1 to i321072 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01073 ret { i32 } %.fca.0.insert1074}1075 1076declare <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8>) nounwind readnone1077 1078define { i32 } @test__builtin_mips_precequ_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone {1079entry:1080; CHECK: precequ.ph.qbra1081 1082 %0 = bitcast i32 %a0.coerce to <4 x i8>1083 %1 = tail call <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8> %0)1084 %2 = bitcast <2 x i16> %1 to i321085 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01086 ret { i32 } %.fca.0.insert1087}1088 1089declare <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8>) nounwind readnone1090 1091define { i32 } @test__builtin_mips_preceu_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone {1092entry:1093; CHECK: preceu.ph.qbl1094 1095 %0 = bitcast i32 %a0.coerce to <4 x i8>1096 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8> %0)1097 %2 = bitcast <2 x i16> %1 to i321098 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01099 ret { i32 } %.fca.0.insert1100}1101 1102declare <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8>) nounwind readnone1103 1104define { i32 } @test__builtin_mips_preceu_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone {1105entry:1106; CHECK: preceu.ph.qbr1107 1108 %0 = bitcast i32 %a0.coerce to <4 x i8>1109 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8> %0)1110 %2 = bitcast <2 x i16> %1 to i321111 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01112 ret { i32 } %.fca.0.insert1113}1114 1115declare <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8>) nounwind readnone1116 1117define { i32 } @test__builtin_mips_preceu_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone {1118entry:1119; CHECK: preceu.ph.qbla1120 1121 %0 = bitcast i32 %a0.coerce to <4 x i8>1122 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8> %0)1123 %2 = bitcast <2 x i16> %1 to i321124 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01125 ret { i32 } %.fca.0.insert1126}1127 1128declare <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8>) nounwind readnone1129 1130define { i32 } @test__builtin_mips_preceu_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone {1131entry:1132; CHECK: preceu.ph.qbra1133 1134 %0 = bitcast i32 %a0.coerce to <4 x i8>1135 %1 = tail call <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8> %0)1136 %2 = bitcast <2 x i16> %1 to i321137 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 01138 ret { i32 } %.fca.0.insert1139}1140 1141declare <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8>) nounwind readnone1142 1143define { i32 } @test__builtin_mips_repl_qb1(i32 %i0) nounwind readnone {1144entry:1145; CHECK: repl.qb1146 1147 %0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 127)1148 %1 = bitcast <4 x i8> %0 to i321149 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 01150 ret { i32 } %.fca.0.insert1151}1152 1153declare <4 x i8> @llvm.mips.repl.qb(i32) nounwind readnone1154 1155define { i32 } @test__builtin_mips_repl_qb2(i32 %i0, i32 %a0) nounwind readnone {1156entry:1157; CHECK: replv.qb1158 1159 %0 = tail call <4 x i8> @llvm.mips.repl.qb(i32 %a0)1160 %1 = bitcast <4 x i8> %0 to i321161 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 01162 ret { i32 } %.fca.0.insert1163}1164 1165define { i32 } @test__builtin_mips_repl_ph1(i32 %i0) nounwind readnone {1166entry:1167; CHECK: repl.ph1168 1169 %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 0)1170 %1 = bitcast <2 x i16> %0 to i321171 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 01172 ret { i32 } %.fca.0.insert1173}1174 1175define { i32 } @test__builtin_mips_repl_ph2(i32 %i0) nounwind readnone {1176entry:1177; CHECK: repl.ph1178 1179 %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 -2)1180 %1 = bitcast <2 x i16> %0 to i321181 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 01182 ret { i32 } %.fca.0.insert1183}1184 1185declare <2 x i16> @llvm.mips.repl.ph(i32) nounwind readnone1186 1187define { i32 } @test__builtin_mips_repl_ph3(i32 %i0, i32 %a0) nounwind readnone {1188entry:1189; CHECK: replv.ph1190 1191 %0 = tail call <2 x i16> @llvm.mips.repl.ph(i32 %a0)1192 %1 = bitcast <2 x i16> %0 to i321193 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 01194 ret { i32 } %.fca.0.insert1195}1196 1197define i32 @test__builtin_mips_bitrev1(i32 %i0, i32 %a0) nounwind readnone {1198entry:1199; CHECK: bitrev ${{[0-9]+}}1200 1201 %0 = tail call i32 @llvm.mips.bitrev(i32 %a0)1202 ret i32 %01203}1204 1205declare i32 @llvm.mips.bitrev(i32) nounwind readnone1206 1207define i32 @test__builtin_mips_lbux1(i32 %i0, ptr %a0, i32 %a1) nounwind readonly {1208entry:1209; CHECK: lbux ${{[0-9]+}}1210 1211 %0 = tail call i32 @llvm.mips.lbux(ptr %a0, i32 %a1)1212 ret i32 %01213}1214 1215declare i32 @llvm.mips.lbux(ptr, i32) nounwind readonly1216 1217define i32 @test__builtin_mips_lhx1(i32 %i0, ptr %a0, i32 %a1) nounwind readonly {1218entry:1219; CHECK: lhx ${{[0-9]+}}1220 1221 %0 = tail call i32 @llvm.mips.lhx(ptr %a0, i32 %a1)1222 ret i32 %01223}1224 1225declare i32 @llvm.mips.lhx(ptr, i32) nounwind readonly1226 1227define i32 @test__builtin_mips_lwx1(i32 %i0, ptr %a0, i32 %a1) nounwind readonly {1228entry:1229; CHECK: lwx ${{[0-9]+}}1230 1231 %0 = tail call i32 @llvm.mips.lwx(ptr %a0, i32 %a1)1232 ret i32 %01233}1234 1235declare i32 @llvm.mips.lwx(ptr, i32) nounwind readonly1236 1237define i32 @test__builtin_mips_wrdsp1(i32 %i0, i32 %a0) nounwind {1238entry:1239; CHECK: wrdsp ${{[0-9]+}}1240; CHECK: rddsp ${{[0-9]+}}1241 1242 tail call void @llvm.mips.wrdsp(i32 %a0, i32 31)1243 %0 = tail call i32 @llvm.mips.rddsp(i32 31)1244 ret i32 %01245}1246 1247declare void @llvm.mips.wrdsp(i32, i32) nounwind1248