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1; RUN: llc -mtriple=mipsel -mattr=+dspr2 < %s | FileCheck %s2 3define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {4entry:5; CHECK: dpa.w.ph6 7 %1 = bitcast i32 %a1.coerce to <2 x i16>8 %2 = bitcast i32 %a2.coerce to <2 x i16>9 %3 = tail call i64 @llvm.mips.dpa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)10 ret i64 %311}12 13declare i64 @llvm.mips.dpa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone14 15define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {16entry:17; CHECK: dps.w.ph18 19 %1 = bitcast i32 %a1.coerce to <2 x i16>20 %2 = bitcast i32 %a2.coerce to <2 x i16>21 %3 = tail call i64 @llvm.mips.dps.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)22 ret i64 %323}24 25declare i64 @llvm.mips.dps.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone26 27define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {28entry:29; CHECK: mulsa.w.ph30 31 %1 = bitcast i32 %a1.coerce to <2 x i16>32 %2 = bitcast i32 %a2.coerce to <2 x i16>33 %3 = tail call i64 @llvm.mips.mulsa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)34 ret i64 %335}36 37declare i64 @llvm.mips.mulsa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone38 39define i64 @test__builtin_mips_dpax_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {40entry:41; CHECK: dpax.w.ph42 43 %1 = bitcast i32 %a1.coerce to <2 x i16>44 %2 = bitcast i32 %a2.coerce to <2 x i16>45 %3 = tail call i64 @llvm.mips.dpax.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)46 ret i64 %347}48 49declare i64 @llvm.mips.dpax.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone50 51define i64 @test__builtin_mips_dpsx_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {52entry:53; CHECK: dpsx.w.ph54 55 %1 = bitcast i32 %a1.coerce to <2 x i16>56 %2 = bitcast i32 %a2.coerce to <2 x i16>57 %3 = tail call i64 @llvm.mips.dpsx.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)58 ret i64 %359}60 61declare i64 @llvm.mips.dpsx.w.ph(i64, <2 x i16>, <2 x i16>) nounwind readnone62 63define i64 @test__builtin_mips_dpaqx_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {64entry:65; CHECK: dpaqx_s.w.ph66 67 %1 = bitcast i32 %a1.coerce to <2 x i16>68 %2 = bitcast i32 %a2.coerce to <2 x i16>69 %3 = tail call i64 @llvm.mips.dpaqx.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)70 ret i64 %371}72 73declare i64 @llvm.mips.dpaqx.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind74 75define i64 @test__builtin_mips_dpaqx_sa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {76entry:77; CHECK: dpaqx_sa.w.ph78 79 %1 = bitcast i32 %a1.coerce to <2 x i16>80 %2 = bitcast i32 %a2.coerce to <2 x i16>81 %3 = tail call i64 @llvm.mips.dpaqx.sa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)82 ret i64 %383}84 85declare i64 @llvm.mips.dpaqx.sa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind86 87define i64 @test__builtin_mips_dpsqx_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {88entry:89; CHECK: dpsqx_s.w.ph90 91 %1 = bitcast i32 %a1.coerce to <2 x i16>92 %2 = bitcast i32 %a2.coerce to <2 x i16>93 %3 = tail call i64 @llvm.mips.dpsqx.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)94 ret i64 %395}96 97declare i64 @llvm.mips.dpsqx.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind98 99define i64 @test__builtin_mips_dpsqx_sa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {100entry:101; CHECK: dpsqx_sa.w.ph102 103 %1 = bitcast i32 %a1.coerce to <2 x i16>104 %2 = bitcast i32 %a2.coerce to <2 x i16>105 %3 = tail call i64 @llvm.mips.dpsqx.sa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)106 ret i64 %3107}108 109declare i64 @llvm.mips.dpsqx.sa.w.ph(i64, <2 x i16>, <2 x i16>) nounwind110 111define { i32 } @test__builtin_mips_addu_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {112entry:113; CHECK: addu.ph114 115 %0 = bitcast i32 %a0.coerce to <2 x i16>116 %1 = bitcast i32 %a1.coerce to <2 x i16>117 %2 = tail call <2 x i16> @llvm.mips.addu.ph(<2 x i16> %0, <2 x i16> %1)118 %3 = bitcast <2 x i16> %2 to i32119 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0120 ret { i32 } %.fca.0.insert121}122 123declare <2 x i16> @llvm.mips.addu.ph(<2 x i16>, <2 x i16>) nounwind124 125define { i32 } @test__builtin_mips_addu_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {126entry:127; CHECK: addu_s.ph128 129 %0 = bitcast i32 %a0.coerce to <2 x i16>130 %1 = bitcast i32 %a1.coerce to <2 x i16>131 %2 = tail call <2 x i16> @llvm.mips.addu.s.ph(<2 x i16> %0, <2 x i16> %1)132 %3 = bitcast <2 x i16> %2 to i32133 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0134 ret { i32 } %.fca.0.insert135}136 137declare <2 x i16> @llvm.mips.addu.s.ph(<2 x i16>, <2 x i16>) nounwind138 139define { i32 } @test__builtin_mips_mulq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {140entry:141; CHECK: mulq_s.ph142 143 %0 = bitcast i32 %a0.coerce to <2 x i16>144 %1 = bitcast i32 %a1.coerce to <2 x i16>145 %2 = tail call <2 x i16> @llvm.mips.mulq.s.ph(<2 x i16> %0, <2 x i16> %1)146 %3 = bitcast <2 x i16> %2 to i32147 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0148 ret { i32 } %.fca.0.insert149}150 151declare <2 x i16> @llvm.mips.mulq.s.ph(<2 x i16>, <2 x i16>) nounwind152 153define { i32 } @test__builtin_mips_subu_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {154entry:155; CHECK: subu.ph156 157 %0 = bitcast i32 %a0.coerce to <2 x i16>158 %1 = bitcast i32 %a1.coerce to <2 x i16>159 %2 = tail call <2 x i16> @llvm.mips.subu.ph(<2 x i16> %0, <2 x i16> %1)160 %3 = bitcast <2 x i16> %2 to i32161 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0162 ret { i32 } %.fca.0.insert163}164 165declare <2 x i16> @llvm.mips.subu.ph(<2 x i16>, <2 x i16>) nounwind166 167define { i32 } @test__builtin_mips_subu_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {168entry:169; CHECK: subu_s.ph170 171 %0 = bitcast i32 %a0.coerce to <2 x i16>172 %1 = bitcast i32 %a1.coerce to <2 x i16>173 %2 = tail call <2 x i16> @llvm.mips.subu.s.ph(<2 x i16> %0, <2 x i16> %1)174 %3 = bitcast <2 x i16> %2 to i32175 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0176 ret { i32 } %.fca.0.insert177}178 179declare <2 x i16> @llvm.mips.subu.s.ph(<2 x i16>, <2 x i16>) nounwind180 181define i32 @test__builtin_mips_cmpgdu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {182entry:183; CHECK: cmpgdu.eq.qb184 185 %0 = bitcast i32 %a0.coerce to <4 x i8>186 %1 = bitcast i32 %a1.coerce to <4 x i8>187 %2 = tail call i32 @llvm.mips.cmpgdu.eq.qb(<4 x i8> %0, <4 x i8> %1)188 ret i32 %2189}190 191declare i32 @llvm.mips.cmpgdu.eq.qb(<4 x i8>, <4 x i8>) nounwind192 193define i32 @test__builtin_mips_cmpgdu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {194entry:195; CHECK: cmpgdu.lt.qb196 197 %0 = bitcast i32 %a0.coerce to <4 x i8>198 %1 = bitcast i32 %a1.coerce to <4 x i8>199 %2 = tail call i32 @llvm.mips.cmpgdu.lt.qb(<4 x i8> %0, <4 x i8> %1)200 ret i32 %2201}202 203declare i32 @llvm.mips.cmpgdu.lt.qb(<4 x i8>, <4 x i8>) nounwind204 205define i32 @test__builtin_mips_cmpgdu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {206entry:207; CHECK: cmpgdu.le.qb208 209 %0 = bitcast i32 %a0.coerce to <4 x i8>210 %1 = bitcast i32 %a1.coerce to <4 x i8>211 %2 = tail call i32 @llvm.mips.cmpgdu.le.qb(<4 x i8> %0, <4 x i8> %1)212 ret i32 %2213}214 215declare i32 @llvm.mips.cmpgdu.le.qb(<4 x i8>, <4 x i8>) nounwind216 217define { i32 } @test__builtin_mips_precr_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {218entry:219; CHECK: precr.qb.ph220 221 %0 = bitcast i32 %a0.coerce to <2 x i16>222 %1 = bitcast i32 %a1.coerce to <2 x i16>223 %2 = tail call <4 x i8> @llvm.mips.precr.qb.ph(<2 x i16> %0, <2 x i16> %1)224 %3 = bitcast <4 x i8> %2 to i32225 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0226 ret { i32 } %.fca.0.insert227}228 229declare <4 x i8> @llvm.mips.precr.qb.ph(<2 x i16>, <2 x i16>) nounwind230 231define { i32 } @test__builtin_mips_precr_sra_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {232entry:233; CHECK: precr_sra.ph.w234 235 %0 = tail call <2 x i16> @llvm.mips.precr.sra.ph.w(i32 %a0, i32 %a1, i32 15)236 %1 = bitcast <2 x i16> %0 to i32237 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0238 ret { i32 } %.fca.0.insert239}240 241declare <2 x i16> @llvm.mips.precr.sra.ph.w(i32, i32, i32) nounwind readnone242 243define { i32 } @test__builtin_mips_precr_sra_r_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {244entry:245; CHECK: precr_sra_r.ph.w246 247 %0 = tail call <2 x i16> @llvm.mips.precr.sra.r.ph.w(i32 %a0, i32 %a1, i32 15)248 %1 = bitcast <2 x i16> %0 to i32249 %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0250 ret { i32 } %.fca.0.insert251}252 253declare <2 x i16> @llvm.mips.precr.sra.r.ph.w(i32, i32, i32) nounwind readnone254 255define { i32 } @test__builtin_mips_shra_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {256entry:257; CHECK: shra.qb258 259 %0 = bitcast i32 %a0.coerce to <4 x i8>260 %1 = tail call <4 x i8> @llvm.mips.shra.qb(<4 x i8> %0, i32 3)261 %2 = bitcast <4 x i8> %1 to i32262 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0263 ret { i32 } %.fca.0.insert264}265 266declare <4 x i8> @llvm.mips.shra.qb(<4 x i8>, i32) nounwind readnone267 268define { i32 } @test__builtin_mips_shra_r_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {269entry:270; CHECK: shra_r.qb271 272 %0 = bitcast i32 %a0.coerce to <4 x i8>273 %1 = tail call <4 x i8> @llvm.mips.shra.r.qb(<4 x i8> %0, i32 3)274 %2 = bitcast <4 x i8> %1 to i32275 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0276 ret { i32 } %.fca.0.insert277}278 279declare <4 x i8> @llvm.mips.shra.r.qb(<4 x i8>, i32) nounwind readnone280 281define { i32 } @test__builtin_mips_shra_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {282entry:283; CHECK: shrav.qb284 285 %0 = bitcast i32 %a0.coerce to <4 x i8>286 %1 = tail call <4 x i8> @llvm.mips.shra.qb(<4 x i8> %0, i32 %a1)287 %2 = bitcast <4 x i8> %1 to i32288 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0289 ret { i32 } %.fca.0.insert290}291 292define { i32 } @test__builtin_mips_shra_r_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {293entry:294; CHECK: shrav_r.qb295 296 %0 = bitcast i32 %a0.coerce to <4 x i8>297 %1 = tail call <4 x i8> @llvm.mips.shra.r.qb(<4 x i8> %0, i32 %a1)298 %2 = bitcast <4 x i8> %1 to i32299 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0300 ret { i32 } %.fca.0.insert301}302 303define { i32 } @test__builtin_mips_shrl_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone {304entry:305; CHECK: shrl.ph306 307 %0 = bitcast i32 %a0.coerce to <2 x i16>308 %1 = tail call <2 x i16> @llvm.mips.shrl.ph(<2 x i16> %0, i32 7)309 %2 = bitcast <2 x i16> %1 to i32310 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0311 ret { i32 } %.fca.0.insert312}313 314declare <2 x i16> @llvm.mips.shrl.ph(<2 x i16>, i32) nounwind readnone315 316define { i32 } @test__builtin_mips_shrl_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {317entry:318; CHECK: shrlv.ph319 320 %0 = bitcast i32 %a0.coerce to <2 x i16>321 %1 = tail call <2 x i16> @llvm.mips.shrl.ph(<2 x i16> %0, i32 %a1)322 %2 = bitcast <2 x i16> %1 to i32323 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0324 ret { i32 } %.fca.0.insert325}326 327define { i32 } @test__builtin_mips_absq_s_qb1(i32 %i0, i32 %a0.coerce) nounwind {328entry:329; CHECK: absq_s.qb330 331 %0 = bitcast i32 %a0.coerce to <4 x i8>332 %1 = tail call <4 x i8> @llvm.mips.absq.s.qb(<4 x i8> %0)333 %2 = bitcast <4 x i8> %1 to i32334 %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0335 ret { i32 } %.fca.0.insert336}337 338declare <4 x i8> @llvm.mips.absq.s.qb(<4 x i8>) nounwind339 340define { i32 } @test__builtin_mips_mul_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {341entry:342; CHECK: mul.ph343 344 %0 = bitcast i32 %a0.coerce to <2 x i16>345 %1 = bitcast i32 %a1.coerce to <2 x i16>346 %2 = tail call <2 x i16> @llvm.mips.mul.ph(<2 x i16> %0, <2 x i16> %1)347 %3 = bitcast <2 x i16> %2 to i32348 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0349 ret { i32 } %.fca.0.insert350}351 352declare <2 x i16> @llvm.mips.mul.ph(<2 x i16>, <2 x i16>) nounwind353 354define { i32 } @test__builtin_mips_mul_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {355entry:356; CHECK: mul_s.ph357 358 %0 = bitcast i32 %a0.coerce to <2 x i16>359 %1 = bitcast i32 %a1.coerce to <2 x i16>360 %2 = tail call <2 x i16> @llvm.mips.mul.s.ph(<2 x i16> %0, <2 x i16> %1)361 %3 = bitcast <2 x i16> %2 to i32362 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0363 ret { i32 } %.fca.0.insert364}365 366declare <2 x i16> @llvm.mips.mul.s.ph(<2 x i16>, <2 x i16>) nounwind367 368define i32 @test__builtin_mips_mulq_rs_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {369entry:370; CHECK: mulq_rs.w371 372 %0 = tail call i32 @llvm.mips.mulq.rs.w(i32 %a0, i32 %a1)373 ret i32 %0374}375 376declare i32 @llvm.mips.mulq.rs.w(i32, i32) nounwind377 378define i32 @test__builtin_mips_mulq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {379entry:380; CHECK: mulq_s.w381 382 %0 = tail call i32 @llvm.mips.mulq.s.w(i32 %a0, i32 %a1)383 ret i32 %0384}385 386declare i32 @llvm.mips.mulq.s.w(i32, i32) nounwind387 388define { i32 } @test__builtin_mips_adduh_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {389entry:390; CHECK: adduh.qb391 392 %0 = bitcast i32 %a0.coerce to <4 x i8>393 %1 = bitcast i32 %a1.coerce to <4 x i8>394 %2 = tail call <4 x i8> @llvm.mips.adduh.qb(<4 x i8> %0, <4 x i8> %1)395 %3 = bitcast <4 x i8> %2 to i32396 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0397 ret { i32 } %.fca.0.insert398}399 400declare <4 x i8> @llvm.mips.adduh.qb(<4 x i8>, <4 x i8>) nounwind readnone401 402define { i32 } @test__builtin_mips_adduh_r_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {403entry:404; CHECK: adduh_r.qb405 406 %0 = bitcast i32 %a0.coerce to <4 x i8>407 %1 = bitcast i32 %a1.coerce to <4 x i8>408 %2 = tail call <4 x i8> @llvm.mips.adduh.r.qb(<4 x i8> %0, <4 x i8> %1)409 %3 = bitcast <4 x i8> %2 to i32410 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0411 ret { i32 } %.fca.0.insert412}413 414declare <4 x i8> @llvm.mips.adduh.r.qb(<4 x i8>, <4 x i8>) nounwind readnone415 416define { i32 } @test__builtin_mips_subuh_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {417entry:418; CHECK: subuh.qb419 420 %0 = bitcast i32 %a0.coerce to <4 x i8>421 %1 = bitcast i32 %a1.coerce to <4 x i8>422 %2 = tail call <4 x i8> @llvm.mips.subuh.qb(<4 x i8> %0, <4 x i8> %1)423 %3 = bitcast <4 x i8> %2 to i32424 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0425 ret { i32 } %.fca.0.insert426}427 428declare <4 x i8> @llvm.mips.subuh.qb(<4 x i8>, <4 x i8>) nounwind readnone429 430define { i32 } @test__builtin_mips_subuh_r_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {431entry:432; CHECK: subuh_r.qb433 434 %0 = bitcast i32 %a0.coerce to <4 x i8>435 %1 = bitcast i32 %a1.coerce to <4 x i8>436 %2 = tail call <4 x i8> @llvm.mips.subuh.r.qb(<4 x i8> %0, <4 x i8> %1)437 %3 = bitcast <4 x i8> %2 to i32438 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0439 ret { i32 } %.fca.0.insert440}441 442declare <4 x i8> @llvm.mips.subuh.r.qb(<4 x i8>, <4 x i8>) nounwind readnone443 444define { i32 } @test__builtin_mips_addqh_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {445entry:446; CHECK: addqh.ph447 448 %0 = bitcast i32 %a0.coerce to <2 x i16>449 %1 = bitcast i32 %a1.coerce to <2 x i16>450 %2 = tail call <2 x i16> @llvm.mips.addqh.ph(<2 x i16> %0, <2 x i16> %1)451 %3 = bitcast <2 x i16> %2 to i32452 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0453 ret { i32 } %.fca.0.insert454}455 456declare <2 x i16> @llvm.mips.addqh.ph(<2 x i16>, <2 x i16>) nounwind readnone457 458define { i32 } @test__builtin_mips_addqh_r_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {459entry:460; CHECK: addqh_r.ph461 462 %0 = bitcast i32 %a0.coerce to <2 x i16>463 %1 = bitcast i32 %a1.coerce to <2 x i16>464 %2 = tail call <2 x i16> @llvm.mips.addqh.r.ph(<2 x i16> %0, <2 x i16> %1)465 %3 = bitcast <2 x i16> %2 to i32466 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0467 ret { i32 } %.fca.0.insert468}469 470declare <2 x i16> @llvm.mips.addqh.r.ph(<2 x i16>, <2 x i16>) nounwind readnone471 472define i32 @test__builtin_mips_addqh_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {473entry:474; CHECK: addqh.w475 476 %0 = tail call i32 @llvm.mips.addqh.w(i32 %a0, i32 %a1)477 ret i32 %0478}479 480declare i32 @llvm.mips.addqh.w(i32, i32) nounwind readnone481 482define i32 @test__builtin_mips_addqh_r_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {483entry:484; CHECK: addqh_r.w485 486 %0 = tail call i32 @llvm.mips.addqh.r.w(i32 %a0, i32 %a1)487 ret i32 %0488}489 490declare i32 @llvm.mips.addqh.r.w(i32, i32) nounwind readnone491 492define { i32 } @test__builtin_mips_subqh_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {493entry:494; CHECK: subqh.ph495 496 %0 = bitcast i32 %a0.coerce to <2 x i16>497 %1 = bitcast i32 %a1.coerce to <2 x i16>498 %2 = tail call <2 x i16> @llvm.mips.subqh.ph(<2 x i16> %0, <2 x i16> %1)499 %3 = bitcast <2 x i16> %2 to i32500 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0501 ret { i32 } %.fca.0.insert502}503 504declare <2 x i16> @llvm.mips.subqh.ph(<2 x i16>, <2 x i16>) nounwind readnone505 506define { i32 } @test__builtin_mips_subqh_r_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {507entry:508; CHECK: subqh_r.ph509 510 %0 = bitcast i32 %a0.coerce to <2 x i16>511 %1 = bitcast i32 %a1.coerce to <2 x i16>512 %2 = tail call <2 x i16> @llvm.mips.subqh.r.ph(<2 x i16> %0, <2 x i16> %1)513 %3 = bitcast <2 x i16> %2 to i32514 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0515 ret { i32 } %.fca.0.insert516}517 518declare <2 x i16> @llvm.mips.subqh.r.ph(<2 x i16>, <2 x i16>) nounwind readnone519 520define i32 @test__builtin_mips_subqh_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {521entry:522; CHECK: subqh.w523 524 %0 = tail call i32 @llvm.mips.subqh.w(i32 %a0, i32 %a1)525 ret i32 %0526}527 528declare i32 @llvm.mips.subqh.w(i32, i32) nounwind readnone529 530define i32 @test__builtin_mips_subqh_r_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {531entry:532; CHECK: subqh_r.w533 534 %0 = tail call i32 @llvm.mips.subqh.r.w(i32 %a0, i32 %a1)535 ret i32 %0536}537 538declare i32 @llvm.mips.subqh.r.w(i32, i32) nounwind readnone539 540define i32 @test__builtin_mips_append1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {541entry:542; CHECK: append ${{[0-9]+}}543 544 %0 = tail call i32 @llvm.mips.append(i32 %a0, i32 %a1, i32 15)545 ret i32 %0546}547 548declare i32 @llvm.mips.append(i32, i32, i32) nounwind readnone549 550define i32 @test__builtin_mips_balign1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {551entry:552; CHECK: balign ${{[0-9]+}}553 554 %0 = tail call i32 @llvm.mips.balign(i32 %a0, i32 %a1, i32 1)555 ret i32 %0556}557 558declare i32 @llvm.mips.balign(i32, i32, i32) nounwind readnone559 560define i32 @test__builtin_mips_prepend1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {561entry:562; CHECK: prepend ${{[0-9]+}}563 564 %0 = tail call i32 @llvm.mips.prepend(i32 %a0, i32 %a1, i32 15)565 ret i32 %0566}567 568declare i32 @llvm.mips.prepend(i32, i32, i32) nounwind readnone569