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1; RUN: llc -mtriple=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \2; RUN: --check-prefixes=ASM,ALL3; RUN: llc -mtriple=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \4; RUN: llvm-objdump --no-print-imm-hex -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL5 6; Test that spill and reloads use the dsp "variant" instructions. We use -O07; to use the simple register allocator.8 9; To test the micromips output, we have to take a round trip through the10; object file encoder/decoder as the instruction mapping tables are used to11; support micromips.12 13; FIXME: We should be able to get rid of those instructions with the variable14; value registers.15 16; ALL-LABEL: spill_reload{{>?}}:17 18define <4 x i8> @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) {19entry:20 %c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b)21 %cond = icmp eq i32 %g, 022 br i1 %cond, label %true, label %end23 24; ASM: SWDSP25; ASM: SWDSP26 27; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp)28; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp)29 30true:31 ret <4 x i8> %c32 33; ASM: LWDSP34 35; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)36 37end:38 %d = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %c, <4 x i8> %a)39 ret <4 x i8> %d40 41; ASM: LWDSP42; ASM: LWDSP43 44; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)45; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)46 47}48 49declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind50