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1; RUN: llc < %s -mtriple=mips -mcpu=mips32 | \2; RUN: FileCheck %s -check-prefixes=ALL,32-C3; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | \4; RUN: FileCheck %s -check-prefixes=ALL,32-C5; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | \6; RUN: FileCheck %s -check-prefixes=ALL,32-CMP7; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | \8; RUN: FileCheck %s -check-prefixes=ALL,64-C9; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | \10; RUN: FileCheck %s -check-prefixes=ALL,64-C11; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | \12; RUN: FileCheck %s -check-prefixes=ALL,64-C13; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | \14; RUN: FileCheck %s -check-prefixes=ALL,64-CMP15; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \16; RUN: -check-prefixes=ALL,MM,MM32R317; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \18; RUN: -check-prefixes=ALL,MM,MMR6,MM32R619 20define i32 @false_f32(float %a, float %b) nounwind {21; ALL-LABEL: false_f32:22; 32-C: addiu $2, $zero, 023 24; 32-CMP: addiu $2, $zero, 025 26; 64-C: addiu $2, $zero, 027 28; 64-CMP: addiu $2, $zero, 029 30; MM-DAG: li16 $2, 031 32 %1 = fcmp false float %a, %b33 %2 = zext i1 %1 to i3234 ret i32 %235}36 37define i32 @oeq_f32(float %a, float %b) nounwind {38; ALL-LABEL: oeq_f32:39 40; 32-C-DAG: addiu $2, $zero, 141; 32-C-DAG: c.eq.s $f12, $f1442; 32-C: movf $2, $zero, $fcc043 44; 64-C-DAG: addiu $2, $zero, 145; 64-C-DAG: c.eq.s $f12, $f1346; 64-C: movf $2, $zero, $fcc047 48; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f1449; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]50; 32-CMP-DAG: andi $2, $[[T1]], 151 52; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f1353; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]54; 64-CMP-DAG: andi $2, $[[T1]], 155 56; MM32R3-DAG: li16 $[[T0:[0-9]+]], 057; MM32R3-DAG: li16 $[[T1:[0-9]+]], 158; MM32R3-DAG: c.eq.s $f12, $f1459; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc060 61; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f1462; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]63; MMR6-DAG: andi16 $2, $[[T1]], 164 65 %1 = fcmp oeq float %a, %b66 %2 = zext i1 %1 to i3267 ret i32 %268}69 70define i32 @ogt_f32(float %a, float %b) nounwind {71; ALL-LABEL: ogt_f32:72 73; 32-C-DAG: addiu $2, $zero, 174; 32-C-DAG: c.ule.s $f12, $f1475; 32-C: movt $2, $zero, $fcc076 77; 64-C-DAG: addiu $2, $zero, 178; 64-C-DAG: c.ule.s $f12, $f1379; 64-C: movt $2, $zero, $fcc080 81; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f1282; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]83; 32-CMP-DAG: andi $2, $[[T1]], 184 85; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f1286; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]87; 64-CMP-DAG: andi $2, $[[T1]], 188 89; MM32R3-DAG: li16 $[[T0:[0-9]+]], 090; MM32R3-DAG: li16 $[[T1:[0-9]+]], 191; MM32R3-DAG: c.ule.s $f12, $f1492; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc093 94; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f1295; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]96; MMR6-DAG: andi16 $2, $[[T1]], 197 98 %1 = fcmp ogt float %a, %b99 %2 = zext i1 %1 to i32100 ret i32 %2101}102 103define i32 @oge_f32(float %a, float %b) nounwind {104; ALL-LABEL: oge_f32:105 106; 32-C-DAG: addiu $2, $zero, 1107; 32-C-DAG: c.ult.s $f12, $f14108; 32-C: movt $2, $zero, $fcc0109 110; 64-C-DAG: addiu $2, $zero, 1111; 64-C-DAG: c.ult.s $f12, $f13112; 64-C: movt $2, $zero, $fcc0113 114; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12115; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]116; 32-CMP-DAG: andi $2, $[[T1]], 1117 118; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12119; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]120; 64-CMP-DAG: andi $2, $[[T1]], 1121 122; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0123; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1124; MM32R3-DAG: c.ult.s $f12, $f14125; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0126 127; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12128; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]129; MMR6-DAG: andi16 $2, $[[T1]], 1130 131 %1 = fcmp oge float %a, %b132 %2 = zext i1 %1 to i32133 ret i32 %2134}135 136define i32 @olt_f32(float %a, float %b) nounwind {137; ALL-LABEL: olt_f32:138 139; 32-C-DAG: addiu $2, $zero, 1140; 32-C-DAG: c.olt.s $f12, $f14141; 32-C: movf $2, $zero, $fcc0142 143; 64-C-DAG: addiu $2, $zero, 1144; 64-C-DAG: c.olt.s $f12, $f13145; 64-C: movf $2, $zero, $fcc0146 147; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14148; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]149; 32-CMP-DAG: andi $2, $[[T1]], 1150 151; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13152; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]153; 64-CMP-DAG: andi $2, $[[T1]], 1154 155; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0156; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1157; MM32R3-DAG: c.olt.s $f12, $f14158; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0159 160; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14161; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]162; MMR6-DAG: andi16 $2, $[[T1]], 1163 164 %1 = fcmp olt float %a, %b165 %2 = zext i1 %1 to i32166 ret i32 %2167}168 169define i32 @ole_f32(float %a, float %b) nounwind {170; ALL-LABEL: ole_f32:171 172; 32-C-DAG: addiu $2, $zero, 1173; 32-C-DAG: c.ole.s $f12, $f14174; 32-C: movf $2, $zero, $fcc0175 176; 64-C-DAG: addiu $2, $zero, 1177; 64-C-DAG: c.ole.s $f12, $f13178; 64-C: movf $2, $zero, $fcc0179 180; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14181; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]182; 32-CMP-DAG: andi $2, $[[T1]], 1183 184; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13185; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]186; 64-CMP-DAG: andi $2, $[[T1]], 1187 188; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0189; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1190; MM32R3-DAG: c.ole.s $f12, $f14191; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0192 193; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14194; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]195; MMR6-DAG: andi16 $2, $[[T1]], 1196 197 %1 = fcmp ole float %a, %b198 %2 = zext i1 %1 to i32199 ret i32 %2200}201 202define i32 @one_f32(float %a, float %b) nounwind {203; ALL-LABEL: one_f32:204 205; 32-C-DAG: addiu $2, $zero, 1206; 32-C-DAG: c.ueq.s $f12, $f14207; 32-C: movt $2, $zero, $fcc0208 209; 64-C-DAG: addiu $2, $zero, 1210; 64-C-DAG: c.ueq.s $f12, $f13211; 64-C: movt $2, $zero, $fcc0212 213; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14214; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]215; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]216; 32-CMP-DAG: andi $2, $[[T2]], 1217 218; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13219; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]220; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]221; 64-CMP-DAG: andi $2, $[[T2]], 1222 223; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0224; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1225; MM32R3-DAG: c.ueq.s $f12, $f14226; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0227 228; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14229; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]230; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]231; MMR6-DAG: andi16 $2, $[[T2]], 1232 233 %1 = fcmp one float %a, %b234 %2 = zext i1 %1 to i32235 ret i32 %2236}237 238define i32 @ord_f32(float %a, float %b) nounwind {239; ALL-LABEL: ord_f32:240 241; 32-C-DAG: addiu $2, $zero, 1242; 32-C-DAG: c.un.s $f12, $f14243; 32-C: movt $2, $zero, $fcc0244 245; 64-C-DAG: addiu $2, $zero, 1246; 64-C-DAG: c.un.s $f12, $f13247; 64-C: movt $2, $zero, $fcc0248 249; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14250; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]251; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]252; 32-CMP-DAG: andi $2, $[[T2]], 1253 254; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13255; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]256; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]257; 64-CMP-DAG: andi $2, $[[T2]], 1258 259; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0260; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1261; MM32R3-DAG: c.un.s $f12, $f14262; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0263 264; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14265; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]266; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]267; MMR6-DAG: andi16 $2, $[[T2]], 1268 269 %1 = fcmp ord float %a, %b270 %2 = zext i1 %1 to i32271 ret i32 %2272}273 274define i32 @ueq_f32(float %a, float %b) nounwind {275; ALL-LABEL: ueq_f32:276 277; 32-C-DAG: addiu $2, $zero, 1278; 32-C-DAG: c.ueq.s $f12, $f14279; 32-C: movf $2, $zero, $fcc0280 281; 64-C-DAG: addiu $2, $zero, 1282; 64-C-DAG: c.ueq.s $f12, $f13283; 64-C: movf $2, $zero, $fcc0284 285; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14286; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]287; 32-CMP-DAG: andi $2, $[[T1]], 1288 289; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13290; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]291; 64-CMP-DAG: andi $2, $[[T1]], 1292 293; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0294; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1295; MM32R3-DAG: c.ueq.s $f12, $f14296; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0297 298; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14299; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]300; MMR6-DAG: andi16 $2, $[[T1]], 1301 302 %1 = fcmp ueq float %a, %b303 %2 = zext i1 %1 to i32304 ret i32 %2305}306 307define i32 @ugt_f32(float %a, float %b) nounwind {308; ALL-LABEL: ugt_f32:309 310; 32-C-DAG: addiu $2, $zero, 1311; 32-C-DAG: c.ole.s $f12, $f14312; 32-C: movt $2, $zero, $fcc0313 314; 64-C-DAG: addiu $2, $zero, 1315; 64-C-DAG: c.ole.s $f12, $f13316; 64-C: movt $2, $zero, $fcc0317 318; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12319; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]320; 32-CMP-DAG: andi $2, $[[T1]], 1321 322; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12323; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]324; 64-CMP-DAG: andi $2, $[[T1]], 1325 326; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0327; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1328; MM32R3-DAG: c.ole.s $f12, $f14329; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0330 331; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12332; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]333; MMR6-DAG: andi16 $2, $[[T1]], 1334 335 %1 = fcmp ugt float %a, %b336 %2 = zext i1 %1 to i32337 ret i32 %2338}339 340define i32 @uge_f32(float %a, float %b) nounwind {341; ALL-LABEL: uge_f32:342 343; 32-C-DAG: addiu $2, $zero, 1344; 32-C-DAG: c.olt.s $f12, $f14345; 32-C: movt $2, $zero, $fcc0346 347; 64-C-DAG: addiu $2, $zero, 1348; 64-C-DAG: c.olt.s $f12, $f13349; 64-C: movt $2, $zero, $fcc0350 351; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12352; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]353; 32-CMP-DAG: andi $2, $[[T1]], 1354 355; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12356; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]357; 64-CMP-DAG: andi $2, $[[T1]], 1358 359; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0360; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1361; MM32R3-DAG: c.olt.s $f12, $f14362; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0363 364; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12365; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]366; MMR6-DAG: andi16 $2, $[[T1]], 1367 368 %1 = fcmp uge float %a, %b369 %2 = zext i1 %1 to i32370 ret i32 %2371}372 373define i32 @ult_f32(float %a, float %b) nounwind {374; ALL-LABEL: ult_f32:375 376; 32-C-DAG: addiu $2, $zero, 1377; 32-C-DAG: c.ult.s $f12, $f14378; 32-C: movf $2, $zero, $fcc0379 380; 64-C-DAG: addiu $2, $zero, 1381; 64-C-DAG: c.ult.s $f12, $f13382; 64-C: movf $2, $zero, $fcc0383 384; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14385; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]386; 32-CMP-DAG: andi $2, $[[T1]], 1387 388; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13389; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]390; 64-CMP-DAG: andi $2, $[[T1]], 1391 392; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0393; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1394; MM32R3-DAG: c.ult.s $f12, $f14395; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0396 397; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14398; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]399; MMR6-DAG: andi16 $2, $[[T1]], 1400 401 %1 = fcmp ult float %a, %b402 %2 = zext i1 %1 to i32403 ret i32 %2404}405 406define i32 @ule_f32(float %a, float %b) nounwind {407; ALL-LABEL: ule_f32:408 409; 32-C-DAG: addiu $2, $zero, 1410; 32-C-DAG: c.ule.s $f12, $f14411; 32-C: movf $2, $zero, $fcc0412 413; 64-C-DAG: addiu $2, $zero, 1414; 64-C-DAG: c.ule.s $f12, $f13415; 64-C: movf $2, $zero, $fcc0416 417; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14418; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]419; 32-CMP-DAG: andi $2, $[[T1]], 1420 421; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13422; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]423; 64-CMP-DAG: andi $2, $[[T1]], 1424 425; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0426; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1427; MM32R3-DAG: c.ule.s $f12, $f14428; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0429 430; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14431; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]432; MMR6-DAG: andi16 $2, $[[T1]], 1433 434 %1 = fcmp ule float %a, %b435 %2 = zext i1 %1 to i32436 ret i32 %2437}438 439define i32 @une_f32(float %a, float %b) nounwind {440; ALL-LABEL: une_f32:441 442; 32-C-DAG: addiu $2, $zero, 1443; 32-C-DAG: c.eq.s $f12, $f14444; 32-C: movt $2, $zero, $fcc0445 446; 64-C-DAG: addiu $2, $zero, 1447; 64-C-DAG: c.eq.s $f12, $f13448; 64-C: movt $2, $zero, $fcc0449 450; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14451; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]452; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]453; 32-CMP-DAG: andi $2, $[[T2]], 1454 455; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13456; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]457; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]458; 64-CMP-DAG: andi $2, $[[T2]], 1459 460; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0461; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1462; MM32R3-DAG: c.eq.s $f12, $f14463; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0464 465; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14466; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]467; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]468; MMR6-DAG: andi16 $2, $[[T2]], 1469 470 %1 = fcmp une float %a, %b471 %2 = zext i1 %1 to i32472 ret i32 %2473}474 475define i32 @uno_f32(float %a, float %b) nounwind {476; ALL-LABEL: uno_f32:477 478; 32-C-DAG: addiu $2, $zero, 1479; 32-C-DAG: c.un.s $f12, $f14480; 32-C: movf $2, $zero, $fcc0481 482; 64-C-DAG: addiu $2, $zero, 1483; 64-C-DAG: c.un.s $f12, $f13484; 64-C: movf $2, $zero, $fcc0485 486; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14487; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]488; 32-CMP-DAG: andi $2, $[[T1]], 1489 490; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13491; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]492; 64-CMP-DAG: andi $2, $[[T1]], 1493 494; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0495; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1496; MM32R3-DAG: c.un.s $f12, $f14497; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0498 499; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14500; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]501; MMR6-DAG: andi16 $2, $[[T1]], 1502 503 %1 = fcmp uno float %a, %b504 %2 = zext i1 %1 to i32505 ret i32 %2506}507 508define i32 @true_f32(float %a, float %b) nounwind {509; ALL-LABEL: true_f32:510; 32-C: addiu $2, $zero, 1511 512; 32-CMP: addiu $2, $zero, 1513 514; 64-C: addiu $2, $zero, 1515 516; 64-CMP: addiu $2, $zero, 1517 518; MM-DAG: li16 $2, 1519 520 %1 = fcmp true float %a, %b521 %2 = zext i1 %1 to i32522 ret i32 %2523}524 525define i32 @false_f64(double %a, double %b) nounwind {526; ALL-LABEL: false_f64:527; 32-C: addiu $2, $zero, 0528 529; 32-CMP: addiu $2, $zero, 0530 531; 64-C: addiu $2, $zero, 0532 533; 64-CMP: addiu $2, $zero, 0534 535; MM-DAG: li16 $2, 0536 537 %1 = fcmp false double %a, %b538 %2 = zext i1 %1 to i32539 ret i32 %2540}541 542define i32 @oeq_f64(double %a, double %b) nounwind {543; ALL-LABEL: oeq_f64:544 545; 32-C-DAG: addiu $2, $zero, 1546; 32-C-DAG: c.eq.d $f12, $f14547; 32-C: movf $2, $zero, $fcc0548 549; 64-C-DAG: addiu $2, $zero, 1550; 64-C-DAG: c.eq.d $f12, $f13551; 64-C: movf $2, $zero, $fcc0552 553; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14554; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]555; 32-CMP-DAG: andi $2, $[[T1]], 1556 557; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13558; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]559; 64-CMP-DAG: andi $2, $[[T1]], 1560 561; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0562; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1563; MM32R3-DAG: c.eq.d $f12, $f14564; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0565 566; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14567; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]568; MMR6-DAG: andi16 $2, $[[T1]], 1569 570 %1 = fcmp oeq double %a, %b571 %2 = zext i1 %1 to i32572 ret i32 %2573}574 575define i32 @ogt_f64(double %a, double %b) nounwind {576; ALL-LABEL: ogt_f64:577 578; 32-C-DAG: addiu $2, $zero, 1579; 32-C-DAG: c.ule.d $f12, $f14580; 32-C: movt $2, $zero, $fcc0581 582; 64-C-DAG: addiu $2, $zero, 1583; 64-C-DAG: c.ule.d $f12, $f13584; 64-C: movt $2, $zero, $fcc0585 586; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12587; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]588; 32-CMP-DAG: andi $2, $[[T1]], 1589 590; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12591; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]592; 64-CMP-DAG: andi $2, $[[T1]], 1593 594; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0595; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1596; MM32R3-DAG: c.ule.d $f12, $f14597; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0598 599; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12600; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]601; MMR6-DAG: andi16 $2, $[[T1]], 1602 603 %1 = fcmp ogt double %a, %b604 %2 = zext i1 %1 to i32605 ret i32 %2606}607 608define i32 @oge_f64(double %a, double %b) nounwind {609; ALL-LABEL: oge_f64:610 611; 32-C-DAG: addiu $2, $zero, 1612; 32-C-DAG: c.ult.d $f12, $f14613; 32-C: movt $2, $zero, $fcc0614 615; 64-C-DAG: addiu $2, $zero, 1616; 64-C-DAG: c.ult.d $f12, $f13617; 64-C: movt $2, $zero, $fcc0618 619; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12620; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]621; 32-CMP-DAG: andi $2, $[[T1]], 1622 623; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12624; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]625; 64-CMP-DAG: andi $2, $[[T1]], 1626 627; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0628; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1629; MM32R3-DAG: c.ult.d $f12, $f14630; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0631 632; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12633; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]634; MMR6-DAG: andi16 $2, $[[T1]], 1635 636 %1 = fcmp oge double %a, %b637 %2 = zext i1 %1 to i32638 ret i32 %2639}640 641define i32 @olt_f64(double %a, double %b) nounwind {642; ALL-LABEL: olt_f64:643 644; 32-C-DAG: addiu $2, $zero, 1645; 32-C-DAG: c.olt.d $f12, $f14646; 32-C: movf $2, $zero, $fcc0647 648; 64-C-DAG: addiu $2, $zero, 1649; 64-C-DAG: c.olt.d $f12, $f13650; 64-C: movf $2, $zero, $fcc0651 652; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14653; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]654; 32-CMP-DAG: andi $2, $[[T1]], 1655 656; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13657; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]658; 64-CMP-DAG: andi $2, $[[T1]], 1659 660; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0661; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1662; MM32R3-DAG: c.olt.d $f12, $f14663; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0664 665; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14666; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]667; MMR6-DAG: andi16 $2, $[[T1]], 1668 669 %1 = fcmp olt double %a, %b670 %2 = zext i1 %1 to i32671 ret i32 %2672}673 674define i32 @ole_f64(double %a, double %b) nounwind {675; ALL-LABEL: ole_f64:676 677; 32-C-DAG: addiu $2, $zero, 1678; 32-C-DAG: c.ole.d $f12, $f14679; 32-C: movf $2, $zero, $fcc0680 681; 64-C-DAG: addiu $2, $zero, 1682; 64-C-DAG: c.ole.d $f12, $f13683; 64-C: movf $2, $zero, $fcc0684 685; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14686; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]687; 32-CMP-DAG: andi $2, $[[T1]], 1688 689; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13690; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]691; 64-CMP-DAG: andi $2, $[[T1]], 1692 693; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0694; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1695; MM32R3-DAG: c.ole.d $f12, $f14696; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0697 698; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14699; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]700; MMR6-DAG: andi16 $2, $[[T1]], 1701 702 %1 = fcmp ole double %a, %b703 %2 = zext i1 %1 to i32704 ret i32 %2705}706 707define i32 @one_f64(double %a, double %b) nounwind {708; ALL-LABEL: one_f64:709 710; 32-C-DAG: addiu $2, $zero, 1711; 32-C-DAG: c.ueq.d $f12, $f14712; 32-C: movt $2, $zero, $fcc0713 714; 64-C-DAG: addiu $2, $zero, 1715; 64-C-DAG: c.ueq.d $f12, $f13716; 64-C: movt $2, $zero, $fcc0717 718; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14719; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]720; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]721; 32-CMP-DAG: andi $2, $[[T2]], 1722 723; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13724; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]725; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]726; 64-CMP-DAG: andi $2, $[[T2]], 1727 728; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0729; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1730; MM32R3-DAG: c.ueq.d $f12, $f14731; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0732 733; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14734; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]735; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]736; MMR6-DAG: andi16 $2, $[[T2]], 1737 738 %1 = fcmp one double %a, %b739 %2 = zext i1 %1 to i32740 ret i32 %2741}742 743define i32 @ord_f64(double %a, double %b) nounwind {744; ALL-LABEL: ord_f64:745 746; 32-C-DAG: addiu $2, $zero, 1747; 32-C-DAG: c.un.d $f12, $f14748; 32-C: movt $2, $zero, $fcc0749 750; 64-C-DAG: addiu $2, $zero, 1751; 64-C-DAG: c.un.d $f12, $f13752; 64-C: movt $2, $zero, $fcc0753 754; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14755; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]756; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]757; 32-CMP-DAG: andi $2, $[[T2]], 1758 759; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13760; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]761; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]762; 64-CMP-DAG: andi $2, $[[T2]], 1763 764; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0765; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1766; MM32R3-DAG: c.un.d $f12, $f14767; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0768 769; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14770; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]771; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]772; MMR6-DAG: andi16 $2, $[[T2]], 1773 774 %1 = fcmp ord double %a, %b775 %2 = zext i1 %1 to i32776 ret i32 %2777}778 779define i32 @ueq_f64(double %a, double %b) nounwind {780; ALL-LABEL: ueq_f64:781 782; 32-C-DAG: addiu $2, $zero, 1783; 32-C-DAG: c.ueq.d $f12, $f14784; 32-C: movf $2, $zero, $fcc0785 786; 64-C-DAG: addiu $2, $zero, 1787; 64-C-DAG: c.ueq.d $f12, $f13788; 64-C: movf $2, $zero, $fcc0789 790; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14791; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]792; 32-CMP-DAG: andi $2, $[[T1]], 1793 794; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13795; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]796; 64-CMP-DAG: andi $2, $[[T1]], 1797 798; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0799; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1800; MM32R3-DAG: c.ueq.d $f12, $f14801; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0802 803; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14804; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]805; MMR6-DAG: andi16 $2, $[[T1]], 1806 807 %1 = fcmp ueq double %a, %b808 %2 = zext i1 %1 to i32809 ret i32 %2810}811 812define i32 @ugt_f64(double %a, double %b) nounwind {813; ALL-LABEL: ugt_f64:814 815; 32-C-DAG: addiu $2, $zero, 1816; 32-C-DAG: c.ole.d $f12, $f14817; 32-C: movt $2, $zero, $fcc0818 819; 64-C-DAG: addiu $2, $zero, 1820; 64-C-DAG: c.ole.d $f12, $f13821; 64-C: movt $2, $zero, $fcc0822 823; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12824; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]825; 32-CMP-DAG: andi $2, $[[T1]], 1826 827; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12828; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]829; 64-CMP-DAG: andi $2, $[[T1]], 1830 831; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0832; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1833; MM32R3-DAG: c.ole.d $f12, $f14834; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0835 836; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12837; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]838; MMR6-DAG: andi16 $2, $[[T1]], 1839 840 %1 = fcmp ugt double %a, %b841 %2 = zext i1 %1 to i32842 ret i32 %2843}844 845define i32 @uge_f64(double %a, double %b) nounwind {846; ALL-LABEL: uge_f64:847 848; 32-C-DAG: addiu $2, $zero, 1849; 32-C-DAG: c.olt.d $f12, $f14850; 32-C: movt $2, $zero, $fcc0851 852; 64-C-DAG: addiu $2, $zero, 1853; 64-C-DAG: c.olt.d $f12, $f13854; 64-C: movt $2, $zero, $fcc0855 856; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12857; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]858; 32-CMP-DAG: andi $2, $[[T1]], 1859 860; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12861; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]862; 64-CMP-DAG: andi $2, $[[T1]], 1863 864; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0865; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1866; MM32R3-DAG: c.olt.d $f12, $f14867; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0868 869; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12870; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]871; MMR6-DAG: andi16 $2, $[[T1]], 1872 873 %1 = fcmp uge double %a, %b874 %2 = zext i1 %1 to i32875 ret i32 %2876}877 878define i32 @ult_f64(double %a, double %b) nounwind {879; ALL-LABEL: ult_f64:880 881; 32-C-DAG: addiu $2, $zero, 1882; 32-C-DAG: c.ult.d $f12, $f14883; 32-C: movf $2, $zero, $fcc0884 885; 64-C-DAG: addiu $2, $zero, 1886; 64-C-DAG: c.ult.d $f12, $f13887; 64-C: movf $2, $zero, $fcc0888 889; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14890; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]891; 32-CMP-DAG: andi $2, $[[T1]], 1892 893; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13894; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]895; 64-CMP-DAG: andi $2, $[[T1]], 1896 897; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0898; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1899; MM32R3-DAG: c.ult.d $f12, $f14900; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0901 902; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14903; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]904; MMR6-DAG: andi16 $2, $[[T1]], 1905 906 %1 = fcmp ult double %a, %b907 %2 = zext i1 %1 to i32908 ret i32 %2909}910 911define i32 @ule_f64(double %a, double %b) nounwind {912; ALL-LABEL: ule_f64:913 914; 32-C-DAG: addiu $2, $zero, 1915; 32-C-DAG: c.ule.d $f12, $f14916; 32-C: movf $2, $zero, $fcc0917 918; 64-C-DAG: addiu $2, $zero, 1919; 64-C-DAG: c.ule.d $f12, $f13920; 64-C: movf $2, $zero, $fcc0921 922; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14923; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]924; 32-CMP-DAG: andi $2, $[[T1]], 1925 926; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13927; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]928; 64-CMP-DAG: andi $2, $[[T1]], 1929 930; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0931; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1932; MM32R3-DAG: c.ule.d $f12, $f14933; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0934 935; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14936; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]937; MMR6-DAG: andi16 $2, $[[T1]], 1938 939 %1 = fcmp ule double %a, %b940 %2 = zext i1 %1 to i32941 ret i32 %2942}943 944define i32 @une_f64(double %a, double %b) nounwind {945; ALL-LABEL: une_f64:946 947; 32-C-DAG: addiu $2, $zero, 1948; 32-C-DAG: c.eq.d $f12, $f14949; 32-C: movt $2, $zero, $fcc0950 951; 64-C-DAG: addiu $2, $zero, 1952; 64-C-DAG: c.eq.d $f12, $f13953; 64-C: movt $2, $zero, $fcc0954 955; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14956; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]957; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]958; 32-CMP-DAG: andi $2, $[[T2]], 1959 960; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13961; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]962; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]963; 64-CMP-DAG: andi $2, $[[T2]], 1964 965; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0966; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1967; MM32R3-DAG: c.eq.d $f12, $f14968; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0969 970; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14971; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]972; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]973; MMR6-DAG: andi16 $2, $[[T2]], 1974 975 %1 = fcmp une double %a, %b976 %2 = zext i1 %1 to i32977 ret i32 %2978}979 980define i32 @uno_f64(double %a, double %b) nounwind {981; ALL-LABEL: uno_f64:982 983; 32-C-DAG: addiu $2, $zero, 1984; 32-C-DAG: c.un.d $f12, $f14985; 32-C: movf $2, $zero, $fcc0986 987; 64-C-DAG: addiu $2, $zero, 1988; 64-C-DAG: c.un.d $f12, $f13989; 64-C: movf $2, $zero, $fcc0990 991; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14992; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]993; 32-CMP-DAG: andi $2, $[[T1]], 1994 995; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13996; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]997; 64-CMP-DAG: andi $2, $[[T1]], 1998 999; MM32R3-DAG: li16 $[[T0:[0-9]+]], 01000; MM32R3-DAG: li16 $[[T1:[0-9]+]], 11001; MM32R3-DAG: c.un.d $f12, $f141002; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc01003 1004; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f141005; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]1006; MMR6-DAG: andi16 $2, $[[T1]], 11007 1008 %1 = fcmp uno double %a, %b1009 %2 = zext i1 %1 to i321010 ret i32 %21011}1012 1013define i32 @true_f64(double %a, double %b) nounwind {1014; ALL-LABEL: true_f64:1015; 32-C: addiu $2, $zero, 11016 1017; 32-CMP: addiu $2, $zero, 11018 1019; 64-C: addiu $2, $zero, 11020 1021; 64-CMP: addiu $2, $zero, 11022 1023; MM-DAG: li16 $2, 11024 1025 %1 = fcmp true double %a, %b1026 %2 = zext i1 %1 to i321027 ret i32 %21028}1029 1030; The optimizers sometimes produce setlt instead of setolt/setult.1031define float @bug1_f32(float %angle, float %at) #0 {1032entry:1033; ALL-LABEL: bug1_f32:1034 1035; 32-C-DAG: add.s $[[T0:f[0-9]+]], $f14, $f121036; 32-C-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)(1037; 32-C-DAG: c.ole.s $[[T0]], $[[T1]]1038; 32-C-DAG: bc1t1039 1040; 32-CMP-DAG: add.s $[[T0:f[0-9]+]], $f14, $f121041; 32-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo($CPI32_0)(1042; 32-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]1043; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]1044; FIXME: This instruction is redundant.1045; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 11046; 32-CMP-DAG: bnezc $[[T4]],1047 1048; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f121049; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %lo(.LCPI32_0)(1050; 64-C-DAG: c.ole.s $[[T0]], $[[T1]]1051; 64-C-DAG: bc1t1052 1053; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f121054; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %lo(.LCPI32_0)(1055; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]1056; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]1057; FIXME: This instruction is redundant.1058; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 11059; 64-CMP-DAG: bnezc $[[T4]],1060 1061; MM32R3-DAG: add.s $[[T0:f[0-9]+]], $f14, $f121062; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)1063; MM32R3-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])1064; MM32R3-DAG: c.ole.s $[[T0]], $[[T2]]1065; MM32R3-DAG: bc1t1066 1067; MM32R6-DAG: add.s $[[T0:f[0-9]+]], $f14, $f121068; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)1069; MM32R6-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])1070; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]1071; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]]1072; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 11073; MM32R6-DAG: bnezc $[[T5]],1074 1075 %add = fadd fast float %at, %angle1076 %cmp = fcmp ogt float %add, 1.000000e+001077 br i1 %cmp, label %if.then, label %if.end1078 1079if.then:1080 %sub = fadd fast float %add, -1.000000e+001081 br label %if.end1082 1083if.end:1084 %theta.0 = phi float [ %sub, %if.then ], [ %add, %entry ]1085 ret float %theta.01086}1087 1088; The optimizers sometimes produce setlt instead of setolt/setult.1089define double @bug1_f64(double %angle, double %at) #0 {1090entry:1091; ALL-LABEL: bug1_f64:1092 1093; 32-C-DAG: add.d $[[T0:f[0-9]+]], $f14, $f121094; 32-C-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(1095; 32-C-DAG: c.ole.d $[[T0]], $[[T1]]1096; 32-C-DAG: bc1t1097 1098; 32-CMP-DAG: add.d $[[T0:f[0-9]+]], $f14, $f121099; 32-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(1100; 32-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]1101; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]1102; FIXME: This instruction is redundant.1103; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 11104; 32-CMP-DAG: bnezc $[[T4]],1105 1106; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f121107; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %lo(.LCPI33_0)(1108; 64-C-DAG: c.ole.d $[[T0]], $[[T1]]1109; 64-C-DAG: bc1t1110 1111; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f121112; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo(.LCPI33_0)(1113; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]1114; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]1115; FIXME: This instruction is redundant.1116; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 11117; 64-CMP-DAG: bnezc $[[T4]],1118 1119; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f121120; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)1121; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])1122; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]]1123; MM32R3-DAG: bc1t1124 1125; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f121126; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)1127; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])1128; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]1129; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]]1130; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 11131; MM32R6-DAG: bnezc $[[T5]],1132 1133 %add = fadd fast double %at, %angle1134 %cmp = fcmp ogt double %add, 1.000000e+001135 br i1 %cmp, label %if.then, label %if.end1136 1137if.then:1138 %sub = fadd fast double %add, -1.000000e+001139 br label %if.end1140 1141if.end:1142 %theta.0 = phi double [ %sub, %if.then ], [ %add, %entry ]1143 ret double %theta.01144}1145 1146attributes #0 = { nounwind readnone "no-nans-fp-math"="true" }1147