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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-BE3; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-LE4 5declare i8 @llvm.fshl.i8(i8, i8, i8)6declare i16 @llvm.fshl.i16(i16, i16, i16)7declare i32 @llvm.fshl.i32(i32, i32, i32)8declare i64 @llvm.fshl.i64(i64, i64, i64)9declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)10 11declare i8 @llvm.fshr.i8(i8, i8, i8)12declare i16 @llvm.fshr.i16(i16, i16, i16)13declare i32 @llvm.fshr.i32(i32, i32, i32)14declare i64 @llvm.fshr.i64(i64, i64, i64)15declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)16 17; When first 2 operands match, it's a rotate.18 19define i8 @rotl_i8_const_shift(i8 %x) {20; CHECK-LABEL: rotl_i8_const_shift:21; CHECK: # %bb.0:22; CHECK-NEXT: sll $1, $4, 323; CHECK-NEXT: andi $2, $4, 22424; CHECK-NEXT: srl $2, $2, 525; CHECK-NEXT: jr $ra26; CHECK-NEXT: or $2, $1, $227 %f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)28 ret i8 %f29}30 31define i64 @rotl_i64_const_shift(i64 %x) {32; CHECK-LABEL: rotl_i64_const_shift:33; CHECK: # %bb.0:34; CHECK-NEXT: srl $1, $5, 2935; CHECK-NEXT: sll $2, $4, 336; CHECK-NEXT: or $2, $2, $137; CHECK-NEXT: srl $1, $4, 2938; CHECK-NEXT: sll $3, $5, 339; CHECK-NEXT: jr $ra40; CHECK-NEXT: or $3, $3, $141 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)42 ret i64 %f43}44 45; When first 2 operands match, it's a rotate (by variable amount).46 47define i16 @rotl_i16(i16 %x, i16 %z) {48; CHECK-LABEL: rotl_i16:49; CHECK: # %bb.0:50; CHECK-NEXT: andi $1, $5, 1551; CHECK-NEXT: sllv $1, $4, $152; CHECK-NEXT: negu $2, $553; CHECK-NEXT: andi $2, $2, 1554; CHECK-NEXT: andi $3, $4, 6553555; CHECK-NEXT: srlv $2, $3, $256; CHECK-NEXT: jr $ra57; CHECK-NEXT: or $2, $1, $258 %f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)59 ret i16 %f60}61 62define i32 @rotl_i32(i32 %x, i32 %z) {63; CHECK-LABEL: rotl_i32:64; CHECK: # %bb.0:65; CHECK-NEXT: sllv $1, $4, $566; CHECK-NEXT: negu $2, $567; CHECK-NEXT: srlv $2, $4, $268; CHECK-NEXT: jr $ra69; CHECK-NEXT: or $2, $1, $270 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)71 ret i32 %f72}73 74define i64 @rotl_i64(i64 %x, i64 %z) {75; CHECK-BE-LABEL: rotl_i64:76; CHECK-BE: # %bb.0:77; CHECK-BE-NEXT: srl $1, $7, 578; CHECK-BE-NEXT: andi $1, $1, 179; CHECK-BE-NEXT: move $3, $480; CHECK-BE-NEXT: movn $3, $5, $181; CHECK-BE-NEXT: sllv $2, $3, $782; CHECK-BE-NEXT: movn $5, $4, $183; CHECK-BE-NEXT: srl $1, $5, 184; CHECK-BE-NEXT: not $4, $785; CHECK-BE-NEXT: srlv $1, $1, $486; CHECK-BE-NEXT: or $2, $2, $187; CHECK-BE-NEXT: sllv $1, $5, $788; CHECK-BE-NEXT: srl $3, $3, 189; CHECK-BE-NEXT: srlv $3, $3, $490; CHECK-BE-NEXT: jr $ra91; CHECK-BE-NEXT: or $3, $1, $392;93; CHECK-LE-LABEL: rotl_i64:94; CHECK-LE: # %bb.0:95; CHECK-LE-NEXT: srl $1, $6, 596; CHECK-LE-NEXT: andi $1, $1, 197; CHECK-LE-NEXT: move $3, $498; CHECK-LE-NEXT: movn $3, $5, $199; CHECK-LE-NEXT: sllv $2, $3, $6100; CHECK-LE-NEXT: movn $5, $4, $1101; CHECK-LE-NEXT: srl $1, $5, 1102; CHECK-LE-NEXT: not $4, $6103; CHECK-LE-NEXT: srlv $1, $1, $4104; CHECK-LE-NEXT: or $2, $2, $1105; CHECK-LE-NEXT: sllv $1, $5, $6106; CHECK-LE-NEXT: srl $3, $3, 1107; CHECK-LE-NEXT: srlv $3, $3, $4108; CHECK-LE-NEXT: jr $ra109; CHECK-LE-NEXT: or $3, $1, $3110 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)111 ret i64 %f112}113 114; Vector rotate.115 116define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {117; CHECK-LABEL: rotl_v4i32:118; CHECK: # %bb.0:119; CHECK-NEXT: lw $1, 20($sp)120; CHECK-NEXT: negu $2, $1121; CHECK-NEXT: lw $3, 24($sp)122; CHECK-NEXT: negu $8, $3123; CHECK-NEXT: sllv $9, $6, $3124; CHECK-NEXT: srlv $6, $6, $8125; CHECK-NEXT: sllv $1, $5, $1126; CHECK-NEXT: srlv $3, $5, $2127; CHECK-NEXT: lw $2, 16($sp)128; CHECK-NEXT: sllv $5, $4, $2129; CHECK-NEXT: negu $2, $2130; CHECK-NEXT: srlv $2, $4, $2131; CHECK-NEXT: or $2, $5, $2132; CHECK-NEXT: or $3, $1, $3133; CHECK-NEXT: or $4, $9, $6134; CHECK-NEXT: lw $1, 28($sp)135; CHECK-NEXT: sllv $5, $7, $1136; CHECK-NEXT: negu $1, $1137; CHECK-NEXT: srlv $1, $7, $1138; CHECK-NEXT: jr $ra139; CHECK-NEXT: or $5, $5, $1140 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)141 ret <4 x i32> %f142}143 144; Vector rotate by constant splat amount.145 146define <4 x i32> @rotl_v4i32_rotl_const_shift(<4 x i32> %x) {147; CHECK-LABEL: rotl_v4i32_rotl_const_shift:148; CHECK: # %bb.0:149; CHECK-NEXT: srl $1, $5, 29150; CHECK-NEXT: sll $3, $5, 3151; CHECK-NEXT: srl $2, $4, 29152; CHECK-NEXT: sll $4, $4, 3153; CHECK-NEXT: or $2, $4, $2154; CHECK-NEXT: or $3, $3, $1155; CHECK-NEXT: srl $1, $6, 29156; CHECK-NEXT: sll $4, $6, 3157; CHECK-NEXT: or $4, $4, $1158; CHECK-NEXT: srl $1, $7, 29159; CHECK-NEXT: sll $5, $7, 3160; CHECK-NEXT: jr $ra161; CHECK-NEXT: or $5, $5, $1162 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)163 ret <4 x i32> %f164}165 166; Repeat everything for funnel shift right.167 168; When first 2 operands match, it's a rotate.169 170define i8 @rotr_i8_const_shift(i8 %x) {171; CHECK-LABEL: rotr_i8_const_shift:172; CHECK: # %bb.0:173; CHECK-NEXT: sll $1, $4, 5174; CHECK-NEXT: andi $2, $4, 248175; CHECK-NEXT: srl $2, $2, 3176; CHECK-NEXT: jr $ra177; CHECK-NEXT: or $2, $2, $1178 %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)179 ret i8 %f180}181 182define i32 @rotr_i32_const_shift(i32 %x) {183; CHECK-LABEL: rotr_i32_const_shift:184; CHECK: # %bb.0:185; CHECK-NEXT: sll $1, $4, 29186; CHECK-NEXT: srl $2, $4, 3187; CHECK-NEXT: jr $ra188; CHECK-NEXT: or $2, $2, $1189 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)190 ret i32 %f191}192 193; When first 2 operands match, it's a rotate (by variable amount).194 195define i16 @rotr_i16(i16 %x, i16 %z) {196; CHECK-LABEL: rotr_i16:197; CHECK: # %bb.0:198; CHECK-NEXT: andi $1, $5, 15199; CHECK-NEXT: andi $2, $4, 65535200; CHECK-NEXT: srlv $1, $2, $1201; CHECK-NEXT: negu $2, $5202; CHECK-NEXT: andi $2, $2, 15203; CHECK-NEXT: sllv $2, $4, $2204; CHECK-NEXT: jr $ra205; CHECK-NEXT: or $2, $1, $2206 %f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)207 ret i16 %f208}209 210define i32 @rotr_i32(i32 %x, i32 %z) {211; CHECK-LABEL: rotr_i32:212; CHECK: # %bb.0:213; CHECK-NEXT: srlv $1, $4, $5214; CHECK-NEXT: negu $2, $5215; CHECK-NEXT: sllv $2, $4, $2216; CHECK-NEXT: jr $ra217; CHECK-NEXT: or $2, $1, $2218 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)219 ret i32 %f220}221 222define i64 @rotr_i64(i64 %x, i64 %z) {223; CHECK-BE-LABEL: rotr_i64:224; CHECK-BE: # %bb.0:225; CHECK-BE-NEXT: andi $1, $7, 32226; CHECK-BE-NEXT: move $3, $5227; CHECK-BE-NEXT: movz $3, $4, $1228; CHECK-BE-NEXT: srlv $2, $3, $7229; CHECK-BE-NEXT: movz $4, $5, $1230; CHECK-BE-NEXT: sll $1, $4, 1231; CHECK-BE-NEXT: not $5, $7232; CHECK-BE-NEXT: sllv $1, $1, $5233; CHECK-BE-NEXT: or $2, $1, $2234; CHECK-BE-NEXT: srlv $1, $4, $7235; CHECK-BE-NEXT: sll $3, $3, 1236; CHECK-BE-NEXT: sllv $3, $3, $5237; CHECK-BE-NEXT: jr $ra238; CHECK-BE-NEXT: or $3, $3, $1239;240; CHECK-LE-LABEL: rotr_i64:241; CHECK-LE: # %bb.0:242; CHECK-LE-NEXT: andi $1, $6, 32243; CHECK-LE-NEXT: move $3, $5244; CHECK-LE-NEXT: movz $3, $4, $1245; CHECK-LE-NEXT: srlv $2, $3, $6246; CHECK-LE-NEXT: movz $4, $5, $1247; CHECK-LE-NEXT: sll $1, $4, 1248; CHECK-LE-NEXT: not $5, $6249; CHECK-LE-NEXT: sllv $1, $1, $5250; CHECK-LE-NEXT: or $2, $1, $2251; CHECK-LE-NEXT: srlv $1, $4, $6252; CHECK-LE-NEXT: sll $3, $3, 1253; CHECK-LE-NEXT: sllv $3, $3, $5254; CHECK-LE-NEXT: jr $ra255; CHECK-LE-NEXT: or $3, $3, $1256 %f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)257 ret i64 %f258}259 260; Vector rotate.261 262define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {263; CHECK-LABEL: rotr_v4i32:264; CHECK: # %bb.0:265; CHECK-NEXT: lw $1, 20($sp)266; CHECK-NEXT: negu $2, $1267; CHECK-NEXT: lw $3, 24($sp)268; CHECK-NEXT: negu $8, $3269; CHECK-NEXT: srlv $9, $6, $3270; CHECK-NEXT: sllv $6, $6, $8271; CHECK-NEXT: srlv $1, $5, $1272; CHECK-NEXT: sllv $3, $5, $2273; CHECK-NEXT: lw $2, 16($sp)274; CHECK-NEXT: srlv $5, $4, $2275; CHECK-NEXT: negu $2, $2276; CHECK-NEXT: sllv $2, $4, $2277; CHECK-NEXT: or $2, $5, $2278; CHECK-NEXT: or $3, $1, $3279; CHECK-NEXT: or $4, $9, $6280; CHECK-NEXT: lw $1, 28($sp)281; CHECK-NEXT: srlv $5, $7, $1282; CHECK-NEXT: negu $1, $1283; CHECK-NEXT: sllv $1, $7, $1284; CHECK-NEXT: jr $ra285; CHECK-NEXT: or $5, $5, $1286 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)287 ret <4 x i32> %f288}289 290; Vector rotate by constant splat amount.291 292define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {293; CHECK-LABEL: rotr_v4i32_const_shift:294; CHECK: # %bb.0:295; CHECK-NEXT: sll $1, $5, 29296; CHECK-NEXT: srl $3, $5, 3297; CHECK-NEXT: sll $2, $4, 29298; CHECK-NEXT: srl $4, $4, 3299; CHECK-NEXT: or $2, $4, $2300; CHECK-NEXT: or $3, $3, $1301; CHECK-NEXT: sll $1, $6, 29302; CHECK-NEXT: srl $4, $6, 3303; CHECK-NEXT: or $4, $4, $1304; CHECK-NEXT: sll $1, $7, 29305; CHECK-NEXT: srl $5, $7, 3306; CHECK-NEXT: jr $ra307; CHECK-NEXT: or $5, $5, $1308 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)309 ret <4 x i32> %f310}311 312define i32 @rotl_i32_shift_by_bitwidth(i32 %x) {313; CHECK-LABEL: rotl_i32_shift_by_bitwidth:314; CHECK: # %bb.0:315; CHECK-NEXT: jr $ra316; CHECK-NEXT: move $2, $4317 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32)318 ret i32 %f319}320 321define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {322; CHECK-LABEL: rotr_i32_shift_by_bitwidth:323; CHECK: # %bb.0:324; CHECK-NEXT: jr $ra325; CHECK-NEXT: move $2, $4326 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32)327 ret i32 %f328}329 330define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {331; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:332; CHECK: # %bb.0:333; CHECK-NEXT: move $2, $4334; CHECK-NEXT: move $3, $5335; CHECK-NEXT: move $4, $6336; CHECK-NEXT: jr $ra337; CHECK-NEXT: move $5, $7338 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)339 ret <4 x i32> %f340}341 342define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {343; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:344; CHECK: # %bb.0:345; CHECK-NEXT: move $2, $4346; CHECK-NEXT: move $3, $5347; CHECK-NEXT: move $4, $6348; CHECK-NEXT: jr $ra349; CHECK-NEXT: move $5, $7350 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)351 ret <4 x i32> %f352}353 354