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1; Positive test for inline register constraints2;3; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s4; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck %s5 6define i32 @main() nounwind {7entry:8 9; r with char10;CHECK: #APP11;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 2312;CHECK: #NO_APP13 tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind14 15; r with short16;CHECK: #APP17;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 1318;CHECK: #NO_APP19 tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind20 21; r with int22;CHECK: #APP23;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 324;CHECK: #NO_APP25 tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind26 27; Now c with 1024: make sure register $25 is picked28; CHECK: #APP29; CHECK: addiu $25, ${{[0-9]+}}, 102430; CHECK: #NO_APP31 tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind32 33; Now l with 1024: make sure register lo is picked. We do this by checking the instruction34; after the inline expression for a mflo to pull the value out of lo.35; CHECK: #APP36; CHECK: mtlo ${{[0-9]+}}37; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}38; CHECK: #NO_APP39; CHECK-NEXT: mflo ${{[0-9]+}}40 %bosco = alloca i32, align 441 call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind42 store volatile i32 %4, ptr %bosco, align 443 44; Check the 'l' constraint for 16-bit type.45; CHECK: #APP46; CHECK: mtlo ${{[0-9]+}}47; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}48; CHECK: #NO_APP49; CHECK-NEXT: mflo ${{[0-9]+}}50 %bosco16 = alloca i16, align 451 call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind52 store volatile i16 %5, ptr %bosco16, align 453 54 ret i32 055}56