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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -O3 -mcpu=mips32r2 -mtriple=mipsel-linux-gnu < %s -o - \3; RUN: | FileCheck %s --check-prefixes=MIPS32R24; RUN: llc -O3 -mcpu=mips64r2 -mtriple=mips64el < %s \5; RUN: | FileCheck %s --check-prefixes=MIPS64R26 7define i32 @or_and_shl(i32 %a, i32 %b) {8; MIPS32R2-LABEL: or_and_shl:9; MIPS32R2: # %bb.0: # %entry10; MIPS32R2-NEXT: ins $4, $5, 31, 111; MIPS32R2-NEXT: jr $ra12; MIPS32R2-NEXT: move $2, $413;14; MIPS64R2-LABEL: or_and_shl:15; MIPS64R2: # %bb.0: # %entry16; MIPS64R2-NEXT: sll $2, $4, 017; MIPS64R2-NEXT: sll $1, $5, 018; MIPS64R2-NEXT: ins $2, $1, 31, 119; MIPS64R2-NEXT: jr $ra20; MIPS64R2-NEXT: nop21entry:22 %shl = shl i32 %b, 3123 %and = and i32 %a, 214748364724 %or = or i32 %and, %shl25 ret i32 %or26}27 28define i32 @or_shl_and(i32 %a, i32 %b) {29; MIPS32R2-LABEL: or_shl_and:30; MIPS32R2: # %bb.0: # %entry31; MIPS32R2-NEXT: ins $4, $5, 31, 132; MIPS32R2-NEXT: jr $ra33; MIPS32R2-NEXT: move $2, $434;35; MIPS64R2-LABEL: or_shl_and:36; MIPS64R2: # %bb.0: # %entry37; MIPS64R2-NEXT: sll $2, $4, 038; MIPS64R2-NEXT: sll $1, $5, 039; MIPS64R2-NEXT: ins $2, $1, 31, 140; MIPS64R2-NEXT: jr $ra41; MIPS64R2-NEXT: nop42entry:43 %shl = shl i32 %b, 3144 %and = and i32 %a, 214748364745 %or = or i32 %shl, %and46 ret i32 %or47}48 49define i64 @dinsm(i64 %a, i64 %b) {50; MIPS32R2-LABEL: dinsm:51; MIPS32R2: # %bb.0: # %entry52; MIPS32R2-NEXT: ins $4, $6, 17, 1553; MIPS32R2-NEXT: srl $1, $6, 1554; MIPS32R2-NEXT: sll $2, $7, 1755; MIPS32R2-NEXT: or $3, $2, $156; MIPS32R2-NEXT: jr $ra57; MIPS32R2-NEXT: move $2, $458;59; MIPS64R2-LABEL: dinsm:60; MIPS64R2: # %bb.0: # %entry61; MIPS64R2-NEXT: dinsm $4, $5, 17, 4762; MIPS64R2-NEXT: jr $ra63; MIPS64R2-NEXT: move $2, $464entry:65 %shl = shl i64 %b, 1766 %and = and i64 %a, 13107167 %or = or i64 %shl, %and68 ret i64 %or69}70 71define i64 @dinsu(i64 %a, i64 %b) {72; MIPS32R2-LABEL: dinsu:73; MIPS32R2: # %bb.0: # %entry74; MIPS32R2-NEXT: ins $5, $6, 3, 2975; MIPS32R2-NEXT: move $2, $476; MIPS32R2-NEXT: jr $ra77; MIPS32R2-NEXT: move $3, $578;79; MIPS64R2-LABEL: dinsu:80; MIPS64R2: # %bb.0: # %entry81; MIPS64R2-NEXT: dinsu $4, $5, 35, 2982; MIPS64R2-NEXT: jr $ra83; MIPS64R2-NEXT: move $2, $484entry:85 %shl = shl i64 %b, 3586 %and = and i64 %a, 3435973836787 %or = or i64 %shl, %and88 ret i64 %or89}90