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1; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefixes=ALL,32,32DF2; RUN: llc -mtriple=mipsel -mattr=+single-float < %s | FileCheck %s -check-prefixes=ALL,32,32SF3 4; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,64,64DF5; RUN: llc -mtriple=mips64el -mcpu=mips4 -mattr=+single-float < %s \6; RUN: | FileCheck %s -check-prefixes=ALL,64,64SF7 8; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64,64DF9; RUN: llc -mtriple=mips64el -mcpu=mips64 -mattr=+single-float < %s \10; RUN: | FileCheck %s -check-prefixes=ALL,64,64SF11 12; Test various combinations of 32/64bit GP registers and single/double floating point support.13 14@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 415@i3 = common global ptr null, align 416 17; ALL-LABEL: test_float_int_:18; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]19; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]20; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]21; 64: cvt.s.w $f{{[0-9]+}}, $f[[R0]]22 23define float @test_float_int_(i32 %a) {24entry:25 %conv = sitofp i32 %a to float26 ret float %conv27}28 29; ALL-LABEL: test_double_int_:30; 32DF: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]31; 32DF: cvt.d.w $f{{[0-9]+}}, $f[[R0]]32; 32SF: jal __floatsidf33; 64DF: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]34; 64DF: cvt.d.w $f{{[0-9]+}}, $f[[R0]]35; 64SF: jal __floatsidf36 37define double @test_double_int_(i32 %a) {38entry:39 %conv = sitofp i32 %a to double40 ret double %conv41}42 43; ALL-LABEL: test_float_LL_:44; 32: jal __floatdisf45; 64DF: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]46; 64DF: cvt.s.l $f{{[0-9]+}}, $f[[R0]]47; 64SF: jal __floatdisf48 49define float @test_float_LL_(i64 %a) {50entry:51 %conv = sitofp i64 %a to float52 ret float %conv53}54 55; ALL-LABEL: test_double_LL_:56; 32: jal __floatdidf57; 64DF: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]58; 64DF: cvt.d.l $f{{[0-9]+}}, $f[[R0]]59; 64SF: jal __floatdidf60 61define double @test_double_LL_(i64 %a) {62entry:63 %conv = sitofp i64 %a to double64 ret double %conv65}66