506 lines · plain
1; RUN: llc < %s -mtriple=mips-elf -mcpu=mips2 | FileCheck %s \2; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,PRE43; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 | FileCheck %s \4; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,GP32-CMOV5; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 | FileCheck %s \6; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV7; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 | FileCheck %s \8; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV9; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r5 | FileCheck %s \10; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV11; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 | FileCheck %s \12; RUN: -check-prefixes=ALL,R2-R6,GP3213; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips3 | FileCheck %s \14; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R615; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips4 | FileCheck %s \16; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R617; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s \18; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R619; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r2 | FileCheck %s \20; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R621; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r3 | FileCheck %s \22; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R623; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r5 | FileCheck %s \24; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R625; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r6 | FileCheck %s \26; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R627; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \28; RUN: -check-prefixes=ALL,MMR3,MM3229; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \30; RUN: -check-prefixes=ALL,MMR6,MM3231 32 33; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. 34; This sequence is even better as it's a single instruction. See D25485 for the rest of 35; the cases where this sequence occurs.36 37define signext i1 @add_i1(i1 signext %a, i1 signext %b) {38entry:39; ALL-LABEL: add_i1:40 41 ; NOT-R2-R6: xor $[[T0:[0-9]+]], $4, $542 43 ; R2-R6: xor $[[T0:[0-9]+]], $4, $544 45 ; MMR6: xor $[[T0:[0-9]+]], $4, $546 47 %r = add i1 %a, %b48 ret i1 %r49}50 51define signext i8 @add_i8(i8 signext %a, i8 signext %b) {52entry:53; ALL-LABEL: add_i8:54 55 ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $556 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 2457 ; NOT-R2-R6: sra $2, $[[T0]], 2458 59 ; R2-R6: addu $[[T0:[0-9]+]], $4, $560 ; R2-R6: seb $2, $[[T0:[0-9]+]]61 62 ; MMR6: addu16 $[[T0:[0-9]+]], $4, $563 ; MMR6: seb $2, $[[T0]]64 65 %r = add i8 %a, %b66 ret i8 %r67}68 69define signext i16 @add_i16(i16 signext %a, i16 signext %b) {70entry:71; ALL-LABEL: add_i16:72 73 ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $574 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 1675 ; NOT-R2-R6: sra $2, $[[T0]], 1676 77 ; R2-R6: addu $[[T0:[0-9]+]], $4, $578 ; R2-R6: seh $2, $[[T0]]79 80 ; MMR6: addu16 $[[T0:[0-9]+]], $4, $581 ; MMR6: seh $2, $[[T0]]82 83 %r = add i16 %a, %b84 ret i16 %r85}86 87define signext i32 @add_i32(i32 signext %a, i32 signext %b) {88entry:89; ALL-LABEL: add_i32:90 91 ; NOT-R2-R6: addu $2, $4, $592 ; R2-R6: addu $2, $4, $593 94 ; MMR6: addu16 $[[T0:[0-9]+]], $4, $595 96 %r = add i32 %a, %b97 ret i32 %r98}99 100define signext i64 @add_i64(i64 signext %a, i64 signext %b) {101entry:102; ALL-LABEL: add_i64:103 104 ; GP32-DAG: addu $[[T0:[0-9]+]], $4, $6105 ; GP32-DAG: addu $3, $5, $7106 ; GP32: sltu $[[T1:[0-9]+]], $3, $5107 ; GP32: addu $2, $[[T0]], $[[T1]]108 109 ; GP64: daddu $2, $4, $5110 111 ; MM32-DAG: addu16 $3, $5, $7112 ; MM32-DAG: addu16 $[[T0:[0-9]+]], $4, $6113 ; MM32: sltu $[[T1:[0-9]+]], $3, $5114 ; MM32: addu16 $2, $[[T0]], $[[T1]]115 116 %r = add i64 %a, %b117 ret i64 %r118}119 120define signext i128 @add_i128(i128 signext %a, i128 signext %b) {121entry:122; ALL-LABEL: add_i128:123 124 ; PRE4: move $[[R1:[0-9]+]], $5125 ; PRE4: move $[[R2:[0-9]+]], $4126 ; PRE4: lw $[[R3:[0-9]+]], 24($sp)127 ; PRE4: addu $[[R4:[0-9]+]], $6, $[[R3]]128 ; PRE4: lw $[[R5:[0-9]+]], 28($sp)129 ; PRE4: addu $[[R6:[0-9]+]], $7, $[[R5]]130 ; PRE4: sltu $[[R7:[0-9]+]], $[[R6]], $7131 ; PRE4: addu $[[R8:[0-9]+]], $[[R4]], $[[R7]]132 ; PRE4: xor $[[R9:[0-9]+]], $[[R8]], $6133 ; PRE4: sltiu $[[R10:[0-9]+]], $[[R9]], 1134 ; PRE4: bnez $[[R10]], $BB5_2135 ; PRE4: sltu $[[R7]], $[[R8]], $6136 ; PRE4: lw $[[R12:[0-9]+]], 20($sp)137 ; PRE4: addu $[[R13:[0-9]+]], $[[R1]], $[[R12]]138 ; PRE4: lw $[[R14:[0-9]+]], 16($sp)139 ; PRE4: addu $[[R15:[0-9]+]], $[[R13]], $[[R7]]140 ; PRE4: addu $[[R16:[0-9]+]], $[[R2]], $[[R14]]141 ; PRE4: sltu $[[R17:[0-9]+]], $[[R15]], $[[R13]]142 ; PRE4: sltu $[[R18:[0-9]+]], $[[R13]], $[[R1]]143 ; PRE4: addu $[[R19:[0-9]+]], $[[R16]], $[[R18]]144 ; PRE4: addu $2, $[[R19]], $[[R17]]145 146 ; GP32-CMOV: lw $[[T0:[0-9]+]], 24($sp)147 ; GP32-CMOV: addu $[[T1:[0-9]+]], $6, $[[T0]]148 ; GP32-CMOV: lw $[[T2:[0-9]+]], 28($sp)149 ; GP32-CMOV: addu $[[T3:[0-9]+]], $7, $[[T2]]150 ; GP32-CMOV: sltu $[[T4:[0-9]+]], $[[T3]], $7151 ; GP32-CMOV: addu $[[T5:[0-9]+]], $[[T1]], $[[T4]]152 ; GP32-CMOV: sltu $[[T6:[0-9]+]], $[[T5]], $6153 ; GP32-CMOV: xor $[[T7:[0-9]+]], $[[T5]], $6154 ; GP32-CMOV: movz $[[T8:[0-9]+]], $[[T4]], $[[T7]]155 ; GP32-CMOV: lw $[[T9:[0-9]+]], 20($sp)156 ; GP32-CMOV: addu $[[T10:[0-9]+]], $5, $[[T4]]157 ; GP32-CMOV: addu $[[T11:[0-9]+]], $[[T10]], $[[T8]]158 ; GP32-CMOV: lw $[[T12:[0-9]+]], 16($sp)159 ; GP32-CMOV: sltu $[[T13:[0-9]+]], $[[T11]], $[[T10]]160 ; GP32-CMOV: addu $[[T14:[0-9]+]], $4, $[[T12]]161 ; GP32-CMOV: sltu $[[T15:[0-9]+]], $[[T10]], $5162 ; GP32-CMOV: addu $[[T16:[0-9]+]], $[[T14]], $[[T15]]163 ; GP32-CMOV: addu $[[T17:[0-9]+]], $[[T16]], $[[T13]]164 ; GP32-CMOV: move $4, $[[T5]]165 ; GP32-CMOV: move $5, $[[T3]]166 167 ; GP64: daddu $[[T0:[0-9]+]], $4, $6168 ; GP64: daddu $[[T1:[0-9]+]], $5, $7169 ; GP64: sltu $[[T2:[0-9]+]], $[[T1]], $5170 ; GP64-NOT-R2-R6: dsll $[[T3:[0-9]+]], $[[T2]], 32171 ; GP64-NOT-R2-R6: dsrl $[[T4:[0-9]+]], $[[T3]], 32172 ; GP64-R2-R6: dext $[[T4:[0-9]+]], $[[T2]], 0, 32173 174 ; GP64: daddu $2, $[[T0]], $[[T4]]175 176 ; MMR3: move $[[T1:[0-9]+]], $5177 ; MMR3-DAG: lw $[[T2:[0-9]+]], 32($sp)178 ; MMR3: addu16 $[[T3:[0-9]+]], $6, $[[T2]]179 ; MMR3-DAG: lw $[[T4:[0-9]+]], 36($sp)180 ; MMR3: addu16 $[[T5:[0-9]+]], $7, $[[T4]]181 ; MMR3: sltu $[[T6:[0-9]+]], $[[T5]], $7182 ; MMR3: addu16 $[[T7:[0-9]+]], $[[T3]], $[[T6]]183 ; MMR3: sltu $[[T8:[0-9]+]], $[[T7]], $6184 ; MMR3: xor $[[T9:[0-9]+]], $[[T7]], $6185 ; MMR3: movz $[[T8]], $[[T6]], $[[T9]]186 ; MMR3: lw $[[T10:[0-9]+]], 28($sp)187 ; MMR3: addu16 $[[T11:[0-9]+]], $[[T1]], $[[T10]]188 ; MMR3: addu16 $[[T12:[0-9]+]], $[[T11]], $[[T8]]189 ; MMR3: lw $[[T13:[0-9]+]], 24($sp)190 ; MMR3: sltu $[[T14:[0-9]+]], $[[T12]], $[[T11]]191 ; MMR3: addu16 $[[T15:[0-9]+]], $4, $[[T13]]192 ; MMR3: sltu $[[T16:[0-9]+]], $[[T11]], $[[T1]]193 ; MMR3: addu16 $[[T17:[0-9]+]], $[[T15]], $[[T16]]194 ; MMR3: addu16 $2, $2, $[[T14]]195 196 ; MMR6: move $[[T1:[0-9]+]], $5197 ; MMR6: move $[[T2:[0-9]+]], $4198 ; MMR6: lw $[[T3:[0-9]+]], 32($sp)199 ; MMR6: addu16 $[[T4:[0-9]+]], $6, $[[T3]]200 ; MMR6: lw $[[T5:[0-9]+]], 36($sp)201 ; MMR6: addu16 $[[T6:[0-9]+]], $7, $[[T5]]202 ; MMR6: sltu $[[T7:[0-9]+]], $[[T6]], $7203 ; MMR6: addu16 $[[T8:[0-9]+]], $[[T4]], $7204 ; MMR6: sltu $[[T9:[0-9]+]], $[[T8]], $6205 ; MMR6: xor $[[T10:[0-9]+]], $[[T4]], $6206 ; MMR6: sltiu $[[T11:[0-9]+]], $[[T10]], 1207 ; MMR6: seleqz $[[T12:[0-9]+]], $[[T9]], $[[T11]]208 ; MMR6: selnez $[[T13:[0-9]+]], $[[T7]], $[[T11]]209 ; MMR6: lw $[[T14:[0-9]+]], 24($sp)210 ; MMR6: or $[[T15:[0-9]+]], $[[T13]], $[[T12]]211 ; MMR6: addu16 $[[T16:[0-9]+]], $[[T2]], $[[T14]]212 ; MMR6: lw $[[T17:[0-9]+]], 28($sp)213 ; MMR6: addu16 $[[T18:[0-9]+]], $[[T1]], $[[T17]]214 ; MMR6: addu16 $[[T19:[0-9]+]], $[[T18]], $[[T15]]215 ; MMR6: sltu $[[T20:[0-9]+]], $[[T18]], $[[T1]]216 ; MMR6: sltu $[[T21:[0-9]+]], $[[T17]], $[[T18]]217 ; MMR6: addu16 $2, $[[T16]], $[[T20]]218 ; MMR6: addu16 $2, $[[T20]], $[[T21]]219 220 %r = add i128 %a, %b221 ret i128 %r222}223 224define signext i1 @add_i1_4(i1 signext %a) {225; ALL-LABEL: add_i1_4:226 227 ; ALL: move $2, $4228 229 %r = add i1 4, %a230 ret i1 %r231}232 233define signext i8 @add_i8_4(i8 signext %a) {234; ALL-LABEL: add_i8_4:235 236 ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 24237 ; NOT-R2-R6: lui $[[T1:[0-9]+]], 1024238 ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]]239 ; NOT-R2-R6: sra $2, $[[T0]], 24240 241 ; R2-R6: addiu $[[T0:[0-9]+]], $4, 4242 ; R2-R6: seb $2, $[[T0]]243 244 ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4245 ; MM32: seb $2, $[[T0]]246 247 %r = add i8 4, %a248 ret i8 %r249}250 251define signext i16 @add_i16_4(i16 signext %a) {252; ALL-LABEL: add_i16_4:253 254 ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 16255 ; NOT-R2-R6: lui $[[T1:[0-9]+]], 4256 ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]]257 ; NOT-R2-R6: sra $2, $[[T0]], 16258 259 ; R2-R6: addiu $[[T0:[0-9]+]], $4, 4260 ; R2-R6: seh $2, $[[T0]]261 262 ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4263 ; MM32: seh $2, $[[T0]]264 265 %r = add i16 4, %a266 ret i16 %r267}268 269define signext i32 @add_i32_4(i32 signext %a) {270; ALL-LABEL: add_i32_4:271 272 ; GP32: addiu $2, $4, 4273 274 ; GP64: addiu $2, $4, 4275 276 ; MM32: addiur2 $2, $4, 4277 278 %r = add i32 4, %a279 ret i32 %r280}281 282define signext i64 @add_i64_4(i64 signext %a) {283; ALL-LABEL: add_i64_4:284 285 ; GP32: addiu $3, $5, 4286 ; GP32: sltu $[[T0:[0-9]+]], $3, $5287 ; GP32: addu $2, $4, $[[T0]]288 289 ; MM32: addiur2 $[[T1:[0-9]+]], $5, 4290 ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $5291 ; MM32: addu16 $2, $4, $[[T2]]292 293 ; GP64: daddiu $2, $4, 4294 295 296 %r = add i64 4, %a297 ret i64 %r298}299 300define signext i128 @add_i128_4(i128 signext %a) {301; ALL-LABEL: add_i128_4:302 303 ; PRE4: move $[[T0:[0-9]+]], $5304 ; PRE4: addiu $[[T1:[0-9]+]], $7, 4305 ; PRE4: sltu $[[T2:[0-9]+]], $[[T1]], $7306 ; PRE4: xori $[[T3:[0-9]+]], $[[T2]], 1307 ; PRE4: bnez $[[T3]], $BB[[BB0:[0-9_]+]]308 ; PRE4: addu $[[T4:[0-9]+]], $6, $[[T2]]309 ; PRE4: sltu $[[T5:[0-9]+]], $[[T4]], $6310 ; PRE4; $BB[[BB0:[0-9]+]]:311 ; PRE4: addu $[[T6:[0-9]+]], $[[T0]], $[[T5]]312 ; PRE4: sltu $[[T7:[0-9]+]], $[[T6]], $[[T0]]313 ; PRE4: addu $[[T8:[0-9]+]], $4, $[[T7]]314 ; PRE4: move $4, $[[T4]]315 316 ; GP32-CMOV: addiu $[[T0:[0-9]+]], $7, 4317 ; GP32-CMOV: sltu $[[T1:[0-9]+]], $[[T0]], $7318 ; GP32-CMOV: addu $[[T2:[0-9]+]], $6, $[[T1]]319 ; GP32-CMOV: sltu $[[T3:[0-9]+]], $[[T2]], $6320 ; GP32-CMOV: movz $[[T3]], $[[T1]], $[[T1]]321 ; GP32-CMOV: addu $[[T4:[0-9]+]], $5, $[[T3]]322 ; GP32-CMOV: sltu $[[T5:[0-9]+]], $[[T4]], $5323 ; GP32-CMOV: addu $[[T7:[0-9]+]], $4, $[[T5]]324 ; GP32-CMOV: move $4, $[[T2]]325 ; GP32-CMOV: move $5, $[[T0]]326 327 ; GP64: daddiu $[[T0:[0-9]+]], $5, 4328 ; GP64: sltu $[[T1:[0-9]+]], $[[T0]], $5329 ; GP64-NOT-R2-R6: dsll $[[T2:[0-9]+]], $[[T1]], 32330 ; GP64-NOT-R2-R6: dsrl $[[T3:[0-9]+]], $[[T2]], 32331 ; GP64-R2-R6: dext $[[T3:[0-9]+]], $[[T1]], 0, 32332 333 ; GP64: daddu $2, $4, $[[T3]]334 335 ; MMR3: addiur2 $[[T0:[0-9]+]], $7, 4336 ; MMR3: sltu $[[T1:[0-9]+]], $[[T0]], $7337 ; MMR3: addu16 $[[T2:[0-9]+]], $6, $[[T1]]338 ; MMR3: sltu $[[T3:[0-9]+]], $[[T2]], $6339 ; MMR3: movz $[[T3]], $[[T1]], $[[T1]]340 ; MMR3: addu16 $[[T6:[0-9]+]], $5, $[[T3]]341 ; MMR3: sltu $[[T7:[0-9]+]], $[[T6]], $5342 ; MMR3: addu16 $2, $4, $[[T7]]343 344 ; MMR6: addiur2 $[[T1:[0-9]+]], $7, 4345 ; MMR6: sltu $[[T2:[0-9]+]], $[[T1]], $7346 ; MMR6: xori $[[T3:[0-9]+]], $[[T2]], 1347 ; MMR6: selnez $[[T4:[0-9]+]], $[[T2]], $[[T3]]348 ; MMR6: addu16 $[[T5:[0-9]+]], $6, $[[T2]]349 ; MMR6: sltu $[[T6:[0-9]+]], $[[T5]], $6350 ; MMR6: seleqz $[[T7:[0-9]+]], $[[T6]], $[[T3]]351 ; MMR6: or $[[T8:[0-9]+]], $[[T4]], $[[T7]]352 ; MMR6: addu16 $[[T9:[0-9]+]], $5, $[[T8]]353 ; MMR6: sltu $[[T10:[0-9]+]], $[[T9]], $5354 ; MMR6: addu16 $[[T11:[0-9]+]], $4, $[[T10]]355 ; MMR6: move $4, $7356 ; MMR6: move $5, $[[T1]]357 358 %r = add i128 4, %a359 ret i128 %r360}361 362define signext i1 @add_i1_3(i1 signext %a) {363; ALL-LABEL: add_i1_3:364 ; GP32: not $[[T0:[0-9]+]], $4365 366 ; GP64: not $[[T0:[0-9]+]], $4367 368 ; MMR6: not16 $[[T0:[0-9]+]], $4369 370 %r = add i1 3, %a371 ret i1 %r372}373 374define signext i8 @add_i8_3(i8 signext %a) {375; ALL-LABEL: add_i8_3:376 377 ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 24378 ; NOT-R2-R6: lui $[[T1:[0-9]+]], 768379 ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]]380 ; NOT-R2-R6: sra $2, $[[T0]], 24381 382 ; R2-R6: addiu $[[T0:[0-9]+]], $4, 3383 ; R2-R6: seb $2, $[[T0]]384 385 ; MMR6: addius5 $[[T0:[0-9]+]], 3386 ; MMR6: seb $2, $[[T0]]387 388 %r = add i8 3, %a389 ret i8 %r390}391 392define signext i16 @add_i16_3(i16 signext %a) {393; ALL-LABEL: add_i16_3:394 395 ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 16396 ; NOT-R2-R6: lui $[[T1:[0-9]+]], 3397 ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]]398 ; NOT-R2-R6: sra $2, $[[T0]], 16399 400 ; R2-R6: addiu $[[T0:[0-9]+]], $4, 3401 ; R2-R6: seh $2, $[[T0]]402 403 ; MMR6: addius5 $[[T0:[0-9]+]], 3404 ; MMR6: seh $2, $[[T0]]405 406 %r = add i16 3, %a407 ret i16 %r408}409 410define signext i32 @add_i32_3(i32 signext %a) {411; ALL-LABEL: add_i32_3:412 413 ; NOT-R2-R6: addiu $2, $4, 3414 415 ; R2-R6: addiu $2, $4, 3416 417 ; MMR6: addius5 $[[T0:[0-9]+]], 3418 ; MMR6: move $2, $[[T0]]419 420 %r = add i32 3, %a421 ret i32 %r422}423 424define signext i64 @add_i64_3(i64 signext %a) {425; ALL-LABEL: add_i64_3:426 427 ; GP32: addiu $[[T0:[0-9]+]], $5, 3428 ; GP32: sltu $[[T1:[0-9]+]], $[[T0]], $5429 ; GP32: addu $2, $4, $[[T1]]430 431 ; GP64: daddiu $2, $4, 3432 433 ; MM32: move $[[T1:[0-9]+]], $5434 ; MM32: addius5 $[[T1]], 3435 ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $5436 ; MM32: addu16 $2, $4, $[[T2]]437 438 %r = add i64 3, %a439 ret i64 %r440}441 442define signext i128 @add_i128_3(i128 signext %a) {443; ALL-LABEL: add_i128_3:444 445 ; PRE4: move $[[T0:[0-9]+]], $5446 ; PRE4: addiu $[[T1:[0-9]+]], $7, 3447 ; PRE4: sltu $[[T2:[0-9]+]], $[[T1]], $7448 ; PRE4: xori $[[T3:[0-9]+]], $[[T2]], 1449 ; PRE4: bnez $[[T3]], $BB[[BB0:[0-9_]+]]450 ; PRE4: addu $[[T4:[0-9]+]], $6, $[[T2]]451 ; PRE4: sltu $[[T5:[0-9]+]], $[[T4]], $6452 ; PRE4; $BB[[BB0:[0-9]+]]:453 ; PRE4: addu $[[T6:[0-9]+]], $[[T0]], $[[T5]]454 ; PRE4: sltu $[[T7:[0-9]+]], $[[T6]], $[[T0]]455 ; PRE4: addu $[[T8:[0-9]+]], $4, $[[T7]]456 ; PRE4: move $4, $[[T4]]457 458 ; GP32-CMOV: addiu $[[T0:[0-9]+]], $7, 3459 ; GP32-CMOV: sltu $[[T1:[0-9]+]], $[[T0]], $7460 ; GP32-CMOV: addu $[[T2:[0-9]+]], $6, $[[T1]]461 ; GP32-CMOV: sltu $[[T3:[0-9]+]], $[[T2]], $6462 ; GP32-CMOV: movz $[[T3]], $[[T1]], $[[T1]]463 ; GP32-CMOV: addu $[[T4:[0-9]+]], $5, $[[T3]]464 ; GP32-CMOV: sltu $[[T5:[0-9]+]], $[[T4]], $5465 ; GP32-CMOV: addu $[[T7:[0-9]+]], $4, $[[T5]]466 ; GP32-CMOV: move $4, $[[T2]]467 ; GP32-CMOV: move $5, $[[T0]]468 469 ; GP64: daddiu $[[T0:[0-9]+]], $5, 3470 ; GP64: sltu $[[T1:[0-9]+]], $[[T0]], $5471 472 ; GP64-NOT-R2-R6: dsll $[[T2:[0-9]+]], $[[T1]], 32473 ; GP64-NOT-R2-R6: dsrl $[[T3:[0-9]+]], $[[T2]], 32474 ; GP64-R2-R6: dext $[[T3:[0-9]+]], $[[T1]], 0, 32475 476 ; GP64: daddu $2, $4, $[[T3]]477 478 ; MMR3: move $[[T1:[0-9]+]], $7479 ; MMR3: addius5 $[[T1]], 3480 ; MMR3: sltu $[[T2:[0-9]+]], $[[T1]], $7481 ; MMR3: addu16 $[[T3:[0-9]+]], $6, $[[T2]]482 ; MMR3: sltu $[[T4:[0-9]+]], $[[T3]], $6483 ; MMR3: movz $[[T4]], $[[T2]], $[[T2]]484 ; MMR3: addu16 $[[T5:[0-9]+]], $5, $[[T4]]485 ; MMR3: sltu $[[T6:[0-9]+]], $[[T5]], $5486 ; MMR3: addu16 $2, $4, $[[T6]]487 488 ; MMR6: move $[[T1:[0-9]+]], $7489 ; MMR6: addius5 $[[T1]], 3490 ; MMR6: sltu $[[T2:[0-9]+]], $[[T1]], $7491 ; MMR6: xori $[[T3:[0-9]+]], $[[T2]], 1492 ; MMR6: selnez $[[T4:[0-9]+]], $[[T2]], $[[T3]]493 ; MMR6: addu16 $[[T5:[0-9]+]], $6, $[[T2]]494 ; MMR6: sltu $[[T6:[0-9]+]], $[[T5]], $6495 ; MMR6: seleqz $[[T7:[0-9]+]], $[[T6]], $[[T3]]496 ; MMR6: or $[[T8:[0-9]+]], $[[T4]], $[[T7]]497 ; MMR6: addu16 $[[T9:[0-9]+]], $5, $[[T8]]498 ; MMR6: sltu $[[T10:[0-9]+]], $[[T9]], $5499 ; MMR6: addu16 $[[T11:[0-9]+]], $4, $[[T10]]500 ; MMR6: move $4, $[[T5]]501 ; MMR6: move $5, $[[T1]]502 503 %r = add i128 3, %a504 ret i128 %r505}506