56 lines · plain
1; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS322; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP643; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM4; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP645; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR66 7define double @add_d(double %a, double %b) {8; MIPS32: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D329; MIPS32FP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D6410; MM: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32_MM11; MMFP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM12; MMR6: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM13 %1 = fadd double %a, %b14 ret double %115}16 17define double @sub_d(double %a, double %b) {18; MIPS32: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D3219; MIPS32FP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D6420; MM: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32_MM21; MMFP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM22; MMR6: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM23 %1 = fsub double %a, %b24 ret double %125}26 27define double @mul_d(double %a, double %b) {28; MIPS32: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D3229; MIPS32FP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D6430; MM: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32_MM31; MMFP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM32; MMR6: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM33 %1 = fmul double %a, %b34 ret double %135}36 37define double @div_d(double %a, double %b) {38; MIPS32: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D3239; MIPS32FP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D6440; MM: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32_MM41; MMFP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM42; MMR6: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM43 %1 = fdiv double %a, %b44 ret double %145}46 47define double @fneg(double %a) {48; MIPS32: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D3249; MIPS32FP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D6450; MM: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32_MM51; MMFP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM52; MMR6: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM53 %1 = fsub double -0.000000e+00, %a54 ret double %155}56