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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \3; RUN: -check-prefix=MIPS4; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \5; RUN: -check-prefix=MIPS326; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \7; RUN: -check-prefix=32R28; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \9; RUN: -check-prefix=32R210; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \11; RUN: -check-prefix=32R212; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \13; RUN: -check-prefix=32R614; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \15; RUN: -check-prefix=MIPS316; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \17; RUN: -check-prefix=MIPS6418; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \19; RUN: -check-prefix=MIPS6420; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \21; RUN: -check-prefix=MIPS64R222; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \23; RUN: -check-prefix=MIPS64R224; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \25; RUN: -check-prefix=MIPS64R226; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \27; RUN: -check-prefix=MIPS64R628; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \29; RUN: -check-prefix=MMR330; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \31; RUN: -check-prefix=MMR632 33define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {34; MIPS-LABEL: ashr_i1:35; MIPS: # %bb.0: # %entry36; MIPS-NEXT: jr $ra37; MIPS-NEXT: move $2, $438;39; MIPS32-LABEL: ashr_i1:40; MIPS32: # %bb.0: # %entry41; MIPS32-NEXT: jr $ra42; MIPS32-NEXT: move $2, $443;44; 32R2-LABEL: ashr_i1:45; 32R2: # %bb.0: # %entry46; 32R2-NEXT: jr $ra47; 32R2-NEXT: move $2, $448;49; 32R6-LABEL: ashr_i1:50; 32R6: # %bb.0: # %entry51; 32R6-NEXT: jr $ra52; 32R6-NEXT: move $2, $453;54; MIPS3-LABEL: ashr_i1:55; MIPS3: # %bb.0: # %entry56; MIPS3-NEXT: jr $ra57; MIPS3-NEXT: move $2, $458;59; MIPS64-LABEL: ashr_i1:60; MIPS64: # %bb.0: # %entry61; MIPS64-NEXT: jr $ra62; MIPS64-NEXT: move $2, $463;64; MIPS64R2-LABEL: ashr_i1:65; MIPS64R2: # %bb.0: # %entry66; MIPS64R2-NEXT: jr $ra67; MIPS64R2-NEXT: move $2, $468;69; MIPS64R6-LABEL: ashr_i1:70; MIPS64R6: # %bb.0: # %entry71; MIPS64R6-NEXT: jr $ra72; MIPS64R6-NEXT: move $2, $473;74; MMR3-LABEL: ashr_i1:75; MMR3: # %bb.0: # %entry76; MMR3-NEXT: move $2, $477; MMR3-NEXT: jrc $ra78;79; MMR6-LABEL: ashr_i1:80; MMR6: # %bb.0: # %entry81; MMR6-NEXT: move $2, $482; MMR6-NEXT: jrc $ra83entry:84 %r = ashr i1 %a, %b85 ret i1 %r86}87 88; FIXME: The andi instruction is redundant.89define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {90; MIPS-LABEL: ashr_i8:91; MIPS: # %bb.0: # %entry92; MIPS-NEXT: jr $ra93; MIPS-NEXT: srav $2, $4, $594;95; MIPS32-LABEL: ashr_i8:96; MIPS32: # %bb.0: # %entry97; MIPS32-NEXT: jr $ra98; MIPS32-NEXT: srav $2, $4, $599;100; 32R2-LABEL: ashr_i8:101; 32R2: # %bb.0: # %entry102; 32R2-NEXT: jr $ra103; 32R2-NEXT: srav $2, $4, $5104;105; 32R6-LABEL: ashr_i8:106; 32R6: # %bb.0: # %entry107; 32R6-NEXT: jr $ra108; 32R6-NEXT: srav $2, $4, $5109;110; MIPS3-LABEL: ashr_i8:111; MIPS3: # %bb.0: # %entry112; MIPS3-NEXT: jr $ra113; MIPS3-NEXT: srav $2, $4, $5114;115; MIPS64-LABEL: ashr_i8:116; MIPS64: # %bb.0: # %entry117; MIPS64-NEXT: jr $ra118; MIPS64-NEXT: srav $2, $4, $5119;120; MIPS64R2-LABEL: ashr_i8:121; MIPS64R2: # %bb.0: # %entry122; MIPS64R2-NEXT: jr $ra123; MIPS64R2-NEXT: srav $2, $4, $5124;125; MIPS64R6-LABEL: ashr_i8:126; MIPS64R6: # %bb.0: # %entry127; MIPS64R6-NEXT: jr $ra128; MIPS64R6-NEXT: srav $2, $4, $5129;130; MMR3-LABEL: ashr_i8:131; MMR3: # %bb.0: # %entry132; MMR3-NEXT: andi16 $2, $5, 255133; MMR3-NEXT: jr $ra134; MMR3-NEXT: srav $2, $4, $2135;136; MMR6-LABEL: ashr_i8:137; MMR6: # %bb.0: # %entry138; MMR6-NEXT: andi16 $2, $5, 255139; MMR6-NEXT: srav $2, $4, $2140; MMR6-NEXT: jrc $ra141entry:142 %r = ashr i8 %a, %b143 ret i8 %r144}145 146; FIXME: The andi instruction is redundant.147define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {148; MIPS-LABEL: ashr_i16:149; MIPS: # %bb.0: # %entry150; MIPS-NEXT: jr $ra151; MIPS-NEXT: srav $2, $4, $5152;153; MIPS32-LABEL: ashr_i16:154; MIPS32: # %bb.0: # %entry155; MIPS32-NEXT: jr $ra156; MIPS32-NEXT: srav $2, $4, $5157;158; 32R2-LABEL: ashr_i16:159; 32R2: # %bb.0: # %entry160; 32R2-NEXT: jr $ra161; 32R2-NEXT: srav $2, $4, $5162;163; 32R6-LABEL: ashr_i16:164; 32R6: # %bb.0: # %entry165; 32R6-NEXT: jr $ra166; 32R6-NEXT: srav $2, $4, $5167;168; MIPS3-LABEL: ashr_i16:169; MIPS3: # %bb.0: # %entry170; MIPS3-NEXT: jr $ra171; MIPS3-NEXT: srav $2, $4, $5172;173; MIPS64-LABEL: ashr_i16:174; MIPS64: # %bb.0: # %entry175; MIPS64-NEXT: jr $ra176; MIPS64-NEXT: srav $2, $4, $5177;178; MIPS64R2-LABEL: ashr_i16:179; MIPS64R2: # %bb.0: # %entry180; MIPS64R2-NEXT: jr $ra181; MIPS64R2-NEXT: srav $2, $4, $5182;183; MIPS64R6-LABEL: ashr_i16:184; MIPS64R6: # %bb.0: # %entry185; MIPS64R6-NEXT: jr $ra186; MIPS64R6-NEXT: srav $2, $4, $5187;188; MMR3-LABEL: ashr_i16:189; MMR3: # %bb.0: # %entry190; MMR3-NEXT: andi16 $2, $5, 65535191; MMR3-NEXT: jr $ra192; MMR3-NEXT: srav $2, $4, $2193;194; MMR6-LABEL: ashr_i16:195; MMR6: # %bb.0: # %entry196; MMR6-NEXT: andi16 $2, $5, 65535197; MMR6-NEXT: srav $2, $4, $2198; MMR6-NEXT: jrc $ra199entry:200 %r = ashr i16 %a, %b201 ret i16 %r202}203 204define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {205; MIPS-LABEL: ashr_i32:206; MIPS: # %bb.0: # %entry207; MIPS-NEXT: jr $ra208; MIPS-NEXT: srav $2, $4, $5209;210; MIPS32-LABEL: ashr_i32:211; MIPS32: # %bb.0: # %entry212; MIPS32-NEXT: jr $ra213; MIPS32-NEXT: srav $2, $4, $5214;215; 32R2-LABEL: ashr_i32:216; 32R2: # %bb.0: # %entry217; 32R2-NEXT: jr $ra218; 32R2-NEXT: srav $2, $4, $5219;220; 32R6-LABEL: ashr_i32:221; 32R6: # %bb.0: # %entry222; 32R6-NEXT: jr $ra223; 32R6-NEXT: srav $2, $4, $5224;225; MIPS3-LABEL: ashr_i32:226; MIPS3: # %bb.0: # %entry227; MIPS3-NEXT: jr $ra228; MIPS3-NEXT: srav $2, $4, $5229;230; MIPS64-LABEL: ashr_i32:231; MIPS64: # %bb.0: # %entry232; MIPS64-NEXT: jr $ra233; MIPS64-NEXT: srav $2, $4, $5234;235; MIPS64R2-LABEL: ashr_i32:236; MIPS64R2: # %bb.0: # %entry237; MIPS64R2-NEXT: jr $ra238; MIPS64R2-NEXT: srav $2, $4, $5239;240; MIPS64R6-LABEL: ashr_i32:241; MIPS64R6: # %bb.0: # %entry242; MIPS64R6-NEXT: jr $ra243; MIPS64R6-NEXT: srav $2, $4, $5244;245; MMR3-LABEL: ashr_i32:246; MMR3: # %bb.0: # %entry247; MMR3-NEXT: jr $ra248; MMR3-NEXT: srav $2, $4, $5249;250; MMR6-LABEL: ashr_i32:251; MMR6: # %bb.0: # %entry252; MMR6-NEXT: srav $2, $4, $5253; MMR6-NEXT: jrc $ra254entry:255 %r = ashr i32 %a, %b256 ret i32 %r257}258 259define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {260; MIPS-LABEL: ashr_i64:261; MIPS: # %bb.0: # %entry262; MIPS-NEXT: andi $1, $7, 32263; MIPS-NEXT: bnez $1, $BB4_2264; MIPS-NEXT: srav $3, $4, $7265; MIPS-NEXT: # %bb.1: # %entry266; MIPS-NEXT: srlv $1, $5, $7267; MIPS-NEXT: xori $2, $7, 31268; MIPS-NEXT: sll $4, $4, 1269; MIPS-NEXT: sllv $2, $4, $2270; MIPS-NEXT: or $1, $2, $1271; MIPS-NEXT: move $2, $3272; MIPS-NEXT: jr $ra273; MIPS-NEXT: move $3, $1274; MIPS-NEXT: $BB4_2:275; MIPS-NEXT: jr $ra276; MIPS-NEXT: sra $2, $4, 31277;278; MIPS32-LABEL: ashr_i64:279; MIPS32: # %bb.0: # %entry280; MIPS32-NEXT: srlv $1, $5, $7281; MIPS32-NEXT: xori $2, $7, 31282; MIPS32-NEXT: sll $3, $4, 1283; MIPS32-NEXT: sllv $2, $3, $2284; MIPS32-NEXT: or $3, $2, $1285; MIPS32-NEXT: srav $2, $4, $7286; MIPS32-NEXT: andi $1, $7, 32287; MIPS32-NEXT: movn $3, $2, $1288; MIPS32-NEXT: sra $4, $4, 31289; MIPS32-NEXT: jr $ra290; MIPS32-NEXT: movn $2, $4, $1291;292; 32R2-LABEL: ashr_i64:293; 32R2: # %bb.0: # %entry294; 32R2-NEXT: srlv $1, $5, $7295; 32R2-NEXT: xori $2, $7, 31296; 32R2-NEXT: sll $3, $4, 1297; 32R2-NEXT: sllv $2, $3, $2298; 32R2-NEXT: or $3, $2, $1299; 32R2-NEXT: srav $2, $4, $7300; 32R2-NEXT: andi $1, $7, 32301; 32R2-NEXT: movn $3, $2, $1302; 32R2-NEXT: sra $4, $4, 31303; 32R2-NEXT: jr $ra304; 32R2-NEXT: movn $2, $4, $1305;306; 32R6-LABEL: ashr_i64:307; 32R6: # %bb.0: # %entry308; 32R6-NEXT: srav $1, $4, $7309; 32R6-NEXT: andi $3, $7, 32310; 32R6-NEXT: seleqz $2, $1, $3311; 32R6-NEXT: sra $6, $4, 31312; 32R6-NEXT: selnez $6, $6, $3313; 32R6-NEXT: or $2, $6, $2314; 32R6-NEXT: srlv $5, $5, $7315; 32R6-NEXT: xori $6, $7, 31316; 32R6-NEXT: sll $4, $4, 1317; 32R6-NEXT: sllv $4, $4, $6318; 32R6-NEXT: or $4, $4, $5319; 32R6-NEXT: seleqz $4, $4, $3320; 32R6-NEXT: selnez $1, $1, $3321; 32R6-NEXT: jr $ra322; 32R6-NEXT: or $3, $1, $4323;324; MIPS3-LABEL: ashr_i64:325; MIPS3: # %bb.0: # %entry326; MIPS3-NEXT: jr $ra327; MIPS3-NEXT: dsrav $2, $4, $5328;329; MIPS64-LABEL: ashr_i64:330; MIPS64: # %bb.0: # %entry331; MIPS64-NEXT: jr $ra332; MIPS64-NEXT: dsrav $2, $4, $5333;334; MIPS64R2-LABEL: ashr_i64:335; MIPS64R2: # %bb.0: # %entry336; MIPS64R2-NEXT: jr $ra337; MIPS64R2-NEXT: dsrav $2, $4, $5338;339; MIPS64R6-LABEL: ashr_i64:340; MIPS64R6: # %bb.0: # %entry341; MIPS64R6-NEXT: jr $ra342; MIPS64R6-NEXT: dsrav $2, $4, $5343;344; MMR3-LABEL: ashr_i64:345; MMR3: # %bb.0: # %entry346; MMR3-NEXT: srlv $2, $5, $7347; MMR3-NEXT: xori $1, $7, 31348; MMR3-NEXT: sll16 $3, $4, 1349; MMR3-NEXT: sllv $3, $3, $1350; MMR3-NEXT: or16 $3, $2351; MMR3-NEXT: srav $2, $4, $7352; MMR3-NEXT: andi16 $5, $7, 32353; MMR3-NEXT: movn $3, $2, $5354; MMR3-NEXT: sra $1, $4, 31355; MMR3-NEXT: jr $ra356; MMR3-NEXT: movn $2, $1, $5357;358; MMR6-LABEL: ashr_i64:359; MMR6: # %bb.0: # %entry360; MMR6-NEXT: srav $1, $4, $7361; MMR6-NEXT: andi16 $3, $7, 32362; MMR6-NEXT: seleqz $2, $1, $3363; MMR6-NEXT: sra $6, $4, 31364; MMR6-NEXT: selnez $6, $6, $3365; MMR6-NEXT: or $2, $6, $2366; MMR6-NEXT: srlv $5, $5, $7367; MMR6-NEXT: xori $6, $7, 31368; MMR6-NEXT: sll16 $4, $4, 1369; MMR6-NEXT: sllv $4, $4, $6370; MMR6-NEXT: or $4, $4, $5371; MMR6-NEXT: seleqz $4, $4, $3372; MMR6-NEXT: selnez $1, $1, $3373; MMR6-NEXT: or $3, $1, $4374; MMR6-NEXT: jrc $ra375entry:376 %r = ashr i64 %a, %b377 ret i64 %r378}379 380define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {381; MIPS-LABEL: ashr_i128:382; MIPS: # %bb.0: # %entry383; MIPS-NEXT: addiu $sp, $sp, -32384; MIPS-NEXT: .cfi_def_cfa_offset 32385; MIPS-NEXT: sra $1, $4, 31386; MIPS-NEXT: sw $7, 28($sp)387; MIPS-NEXT: sw $6, 24($sp)388; MIPS-NEXT: sw $5, 20($sp)389; MIPS-NEXT: sw $4, 16($sp)390; MIPS-NEXT: sw $1, 12($sp)391; MIPS-NEXT: sw $1, 8($sp)392; MIPS-NEXT: sw $1, 4($sp)393; MIPS-NEXT: sw $1, 0($sp)394; MIPS-NEXT: addiu $1, $sp, 0395; MIPS-NEXT: addiu $1, $1, 16396; MIPS-NEXT: lw $2, 60($sp)397; MIPS-NEXT: srl $3, $2, 3398; MIPS-NEXT: andi $3, $3, 12399; MIPS-NEXT: subu $1, $1, $3400; MIPS-NEXT: lw $3, 4($1)401; MIPS-NEXT: lw $5, 8($1)402; MIPS-NEXT: srlv $4, $5, $2403; MIPS-NEXT: sll $6, $3, 1404; MIPS-NEXT: andi $7, $2, 31405; MIPS-NEXT: xori $7, $7, 31406; MIPS-NEXT: sllv $6, $6, $7407; MIPS-NEXT: srlv $3, $3, $2408; MIPS-NEXT: lw $8, 0($1)409; MIPS-NEXT: sll $9, $8, 1410; MIPS-NEXT: sllv $9, $9, $7411; MIPS-NEXT: or $3, $3, $9412; MIPS-NEXT: or $4, $4, $6413; MIPS-NEXT: lw $1, 12($1)414; MIPS-NEXT: srlv $1, $1, $2415; MIPS-NEXT: sll $5, $5, 1416; MIPS-NEXT: sllv $5, $5, $7417; MIPS-NEXT: or $5, $1, $5418; MIPS-NEXT: srav $2, $8, $2419; MIPS-NEXT: jr $ra420; MIPS-NEXT: addiu $sp, $sp, 32421;422; MIPS32-LABEL: ashr_i128:423; MIPS32: # %bb.0: # %entry424; MIPS32-NEXT: addiu $sp, $sp, -32425; MIPS32-NEXT: .cfi_def_cfa_offset 32426; MIPS32-NEXT: sra $1, $4, 31427; MIPS32-NEXT: sw $7, 28($sp)428; MIPS32-NEXT: sw $6, 24($sp)429; MIPS32-NEXT: sw $5, 20($sp)430; MIPS32-NEXT: sw $4, 16($sp)431; MIPS32-NEXT: sw $1, 12($sp)432; MIPS32-NEXT: sw $1, 8($sp)433; MIPS32-NEXT: sw $1, 4($sp)434; MIPS32-NEXT: sw $1, 0($sp)435; MIPS32-NEXT: addiu $1, $sp, 0436; MIPS32-NEXT: addiu $1, $1, 16437; MIPS32-NEXT: lw $2, 60($sp)438; MIPS32-NEXT: srl $3, $2, 3439; MIPS32-NEXT: andi $3, $3, 12440; MIPS32-NEXT: subu $1, $1, $3441; MIPS32-NEXT: lw $3, 4($1)442; MIPS32-NEXT: lw $5, 8($1)443; MIPS32-NEXT: srlv $4, $5, $2444; MIPS32-NEXT: sll $6, $3, 1445; MIPS32-NEXT: andi $7, $2, 31446; MIPS32-NEXT: xori $7, $7, 31447; MIPS32-NEXT: sllv $6, $6, $7448; MIPS32-NEXT: srlv $3, $3, $2449; MIPS32-NEXT: lw $8, 0($1)450; MIPS32-NEXT: sll $9, $8, 1451; MIPS32-NEXT: sllv $9, $9, $7452; MIPS32-NEXT: or $3, $3, $9453; MIPS32-NEXT: or $4, $4, $6454; MIPS32-NEXT: lw $1, 12($1)455; MIPS32-NEXT: srlv $1, $1, $2456; MIPS32-NEXT: sll $5, $5, 1457; MIPS32-NEXT: sllv $5, $5, $7458; MIPS32-NEXT: or $5, $1, $5459; MIPS32-NEXT: srav $2, $8, $2460; MIPS32-NEXT: jr $ra461; MIPS32-NEXT: addiu $sp, $sp, 32462;463; 32R2-LABEL: ashr_i128:464; 32R2: # %bb.0: # %entry465; 32R2-NEXT: addiu $sp, $sp, -32466; 32R2-NEXT: .cfi_def_cfa_offset 32467; 32R2-NEXT: sra $1, $4, 31468; 32R2-NEXT: sw $7, 28($sp)469; 32R2-NEXT: sw $6, 24($sp)470; 32R2-NEXT: sw $5, 20($sp)471; 32R2-NEXT: sw $4, 16($sp)472; 32R2-NEXT: sw $1, 12($sp)473; 32R2-NEXT: sw $1, 8($sp)474; 32R2-NEXT: sw $1, 4($sp)475; 32R2-NEXT: sw $1, 0($sp)476; 32R2-NEXT: addiu $1, $sp, 0477; 32R2-NEXT: addiu $1, $1, 16478; 32R2-NEXT: lw $2, 60($sp)479; 32R2-NEXT: srl $3, $2, 3480; 32R2-NEXT: andi $3, $3, 12481; 32R2-NEXT: subu $1, $1, $3482; 32R2-NEXT: lw $3, 4($1)483; 32R2-NEXT: lw $5, 8($1)484; 32R2-NEXT: srlv $4, $5, $2485; 32R2-NEXT: sll $6, $3, 1486; 32R2-NEXT: andi $7, $2, 31487; 32R2-NEXT: xori $7, $7, 31488; 32R2-NEXT: sllv $6, $6, $7489; 32R2-NEXT: srlv $3, $3, $2490; 32R2-NEXT: lw $8, 0($1)491; 32R2-NEXT: sll $9, $8, 1492; 32R2-NEXT: sllv $9, $9, $7493; 32R2-NEXT: or $3, $3, $9494; 32R2-NEXT: or $4, $4, $6495; 32R2-NEXT: lw $1, 12($1)496; 32R2-NEXT: srlv $1, $1, $2497; 32R2-NEXT: sll $5, $5, 1498; 32R2-NEXT: sllv $5, $5, $7499; 32R2-NEXT: or $5, $1, $5500; 32R2-NEXT: srav $2, $8, $2501; 32R2-NEXT: jr $ra502; 32R2-NEXT: addiu $sp, $sp, 32503;504; 32R6-LABEL: ashr_i128:505; 32R6: # %bb.0: # %entry506; 32R6-NEXT: addiu $sp, $sp, -32507; 32R6-NEXT: .cfi_def_cfa_offset 32508; 32R6-NEXT: sra $1, $4, 31509; 32R6-NEXT: sw $7, 28($sp)510; 32R6-NEXT: sw $6, 24($sp)511; 32R6-NEXT: sw $5, 20($sp)512; 32R6-NEXT: sw $4, 16($sp)513; 32R6-NEXT: sw $1, 12($sp)514; 32R6-NEXT: sw $1, 8($sp)515; 32R6-NEXT: sw $1, 4($sp)516; 32R6-NEXT: sw $1, 0($sp)517; 32R6-NEXT: addiu $1, $sp, 0518; 32R6-NEXT: addiu $1, $1, 16519; 32R6-NEXT: lw $2, 60($sp)520; 32R6-NEXT: srl $3, $2, 3521; 32R6-NEXT: andi $3, $3, 12522; 32R6-NEXT: subu $1, $1, $3523; 32R6-NEXT: lw $3, 4($1)524; 32R6-NEXT: lw $5, 8($1)525; 32R6-NEXT: srlv $4, $5, $2526; 32R6-NEXT: sll $6, $3, 1527; 32R6-NEXT: andi $7, $2, 31528; 32R6-NEXT: xori $7, $7, 31529; 32R6-NEXT: sllv $6, $6, $7530; 32R6-NEXT: srlv $3, $3, $2531; 32R6-NEXT: lw $8, 0($1)532; 32R6-NEXT: sll $9, $8, 1533; 32R6-NEXT: sllv $9, $9, $7534; 32R6-NEXT: or $3, $3, $9535; 32R6-NEXT: or $4, $4, $6536; 32R6-NEXT: lw $1, 12($1)537; 32R6-NEXT: srlv $1, $1, $2538; 32R6-NEXT: sll $5, $5, 1539; 32R6-NEXT: sllv $5, $5, $7540; 32R6-NEXT: or $5, $1, $5541; 32R6-NEXT: srav $2, $8, $2542; 32R6-NEXT: jr $ra543; 32R6-NEXT: addiu $sp, $sp, 32544;545; MIPS3-LABEL: ashr_i128:546; MIPS3: # %bb.0: # %entry547; MIPS3-NEXT: sll $2, $7, 0548; MIPS3-NEXT: andi $1, $2, 64549; MIPS3-NEXT: bnez $1, .LBB5_2550; MIPS3-NEXT: dsrav $3, $4, $7551; MIPS3-NEXT: # %bb.1: # %entry552; MIPS3-NEXT: dsrlv $1, $5, $7553; MIPS3-NEXT: dsll $4, $4, 1554; MIPS3-NEXT: xori $2, $2, 63555; MIPS3-NEXT: dsllv $2, $4, $2556; MIPS3-NEXT: or $1, $2, $1557; MIPS3-NEXT: move $2, $3558; MIPS3-NEXT: jr $ra559; MIPS3-NEXT: move $3, $1560; MIPS3-NEXT: .LBB5_2:561; MIPS3-NEXT: jr $ra562; MIPS3-NEXT: dsra $2, $4, 63563;564; MIPS64-LABEL: ashr_i128:565; MIPS64: # %bb.0: # %entry566; MIPS64-NEXT: dsrlv $1, $5, $7567; MIPS64-NEXT: dsll $2, $4, 1568; MIPS64-NEXT: sll $5, $7, 0569; MIPS64-NEXT: xori $3, $5, 63570; MIPS64-NEXT: dsllv $2, $2, $3571; MIPS64-NEXT: or $3, $2, $1572; MIPS64-NEXT: dsrav $2, $4, $7573; MIPS64-NEXT: andi $1, $5, 64574; MIPS64-NEXT: movn $3, $2, $1575; MIPS64-NEXT: dsra $4, $4, 63576; MIPS64-NEXT: jr $ra577; MIPS64-NEXT: movn $2, $4, $1578;579; MIPS64R2-LABEL: ashr_i128:580; MIPS64R2: # %bb.0: # %entry581; MIPS64R2-NEXT: dsrlv $1, $5, $7582; MIPS64R2-NEXT: dsll $2, $4, 1583; MIPS64R2-NEXT: sll $5, $7, 0584; MIPS64R2-NEXT: xori $3, $5, 63585; MIPS64R2-NEXT: dsllv $2, $2, $3586; MIPS64R2-NEXT: or $3, $2, $1587; MIPS64R2-NEXT: dsrav $2, $4, $7588; MIPS64R2-NEXT: andi $1, $5, 64589; MIPS64R2-NEXT: movn $3, $2, $1590; MIPS64R2-NEXT: dsra $4, $4, 63591; MIPS64R2-NEXT: jr $ra592; MIPS64R2-NEXT: movn $2, $4, $1593;594; MIPS64R6-LABEL: ashr_i128:595; MIPS64R6: # %bb.0: # %entry596; MIPS64R6-NEXT: dsrav $1, $4, $7597; MIPS64R6-NEXT: sll $3, $7, 0598; MIPS64R6-NEXT: andi $2, $3, 64599; MIPS64R6-NEXT: sll $6, $2, 0600; MIPS64R6-NEXT: seleqz $2, $1, $6601; MIPS64R6-NEXT: dsra $8, $4, 63602; MIPS64R6-NEXT: selnez $8, $8, $6603; MIPS64R6-NEXT: or $2, $8, $2604; MIPS64R6-NEXT: dsrlv $5, $5, $7605; MIPS64R6-NEXT: dsll $4, $4, 1606; MIPS64R6-NEXT: xori $3, $3, 63607; MIPS64R6-NEXT: dsllv $3, $4, $3608; MIPS64R6-NEXT: or $3, $3, $5609; MIPS64R6-NEXT: seleqz $3, $3, $6610; MIPS64R6-NEXT: selnez $1, $1, $6611; MIPS64R6-NEXT: jr $ra612; MIPS64R6-NEXT: or $3, $1, $3613;614; MMR3-LABEL: ashr_i128:615; MMR3: # %bb.0: # %entry616; MMR3-NEXT: addiusp -40617; MMR3-NEXT: .cfi_def_cfa_offset 40618; MMR3-NEXT: swp $16, 32($sp)619; MMR3-NEXT: .cfi_offset 17, -4620; MMR3-NEXT: .cfi_offset 16, -8621; MMR3-NEXT: sra $1, $4, 31622; MMR3-NEXT: swp $6, 24($sp)623; MMR3-NEXT: swp $4, 16($sp)624; MMR3-NEXT: sw $1, 12($sp)625; MMR3-NEXT: sw $1, 8($sp)626; MMR3-NEXT: sw $1, 4($sp)627; MMR3-NEXT: sw $1, 0($sp)628; MMR3-NEXT: addiur1sp $2, 0629; MMR3-NEXT: addiur2 $2, $2, 16630; MMR3-NEXT: lw $3, 68($sp)631; MMR3-NEXT: srl16 $4, $3, 3632; MMR3-NEXT: andi $4, $4, 12633; MMR3-NEXT: subu16 $5, $2, $4634; MMR3-NEXT: lwp $6, 4($5)635; MMR3-NEXT: andi16 $2, $3, 31636; MMR3-NEXT: srlv $16, $7, $2637; MMR3-NEXT: sll16 $3, $6, 1638; MMR3-NEXT: xori $1, $2, 31639; MMR3-NEXT: sllv $4, $3, $1640; MMR3-NEXT: srlv $6, $6, $2641; MMR3-NEXT: lw16 $17, 0($5)642; MMR3-NEXT: sll16 $3, $17, 1643; MMR3-NEXT: sllv $3, $3, $1644; MMR3-NEXT: or16 $3, $6645; MMR3-NEXT: or16 $4, $16646; MMR3-NEXT: lw16 $5, 12($5)647; MMR3-NEXT: srlv $6, $5, $2648; MMR3-NEXT: sll16 $5, $7, 1649; MMR3-NEXT: sllv $5, $5, $1650; MMR3-NEXT: or16 $5, $6651; MMR3-NEXT: srav $2, $17, $2652; MMR3-NEXT: lwp $16, 32($sp)653; MMR3-NEXT: addiusp 40654; MMR3-NEXT: jrc $ra655;656; MMR6-LABEL: ashr_i128:657; MMR6: # %bb.0: # %entry658; MMR6-NEXT: addiu $sp, $sp, -40659; MMR6-NEXT: .cfi_def_cfa_offset 40660; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill661; MMR6-NEXT: .cfi_offset 16, -4662; MMR6-NEXT: sra $1, $4, 31663; MMR6-NEXT: sw $7, 28($sp)664; MMR6-NEXT: sw $6, 24($sp)665; MMR6-NEXT: sw $5, 20($sp)666; MMR6-NEXT: sw $4, 16($sp)667; MMR6-NEXT: sw $1, 12($sp)668; MMR6-NEXT: sw $1, 8($sp)669; MMR6-NEXT: sw $1, 4($sp)670; MMR6-NEXT: sw $1, 0($sp)671; MMR6-NEXT: addiu $2, $sp, 0672; MMR6-NEXT: addiur2 $2, $2, 16673; MMR6-NEXT: lw $3, 68($sp)674; MMR6-NEXT: srl16 $4, $3, 3675; MMR6-NEXT: andi $4, $4, 12676; MMR6-NEXT: subu16 $2, $2, $4677; MMR6-NEXT: lw16 $4, 4($2)678; MMR6-NEXT: lw16 $5, 8($2)679; MMR6-NEXT: andi16 $6, $3, 31680; MMR6-NEXT: srlv $1, $5, $6681; MMR6-NEXT: sll16 $3, $4, 1682; MMR6-NEXT: xori $7, $6, 31683; MMR6-NEXT: sllv $8, $3, $7684; MMR6-NEXT: srlv $3, $4, $6685; MMR6-NEXT: lw16 $16, 0($2)686; MMR6-NEXT: sll16 $4, $16, 1687; MMR6-NEXT: sllv $4, $4, $7688; MMR6-NEXT: or $3, $3, $4689; MMR6-NEXT: or $4, $1, $8690; MMR6-NEXT: lw16 $2, 12($2)691; MMR6-NEXT: srlv $1, $2, $6692; MMR6-NEXT: sll16 $2, $5, 1693; MMR6-NEXT: sllv $2, $2, $7694; MMR6-NEXT: or $5, $1, $2695; MMR6-NEXT: srav $2, $16, $6696; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload697; MMR6-NEXT: addiu $sp, $sp, 40698; MMR6-NEXT: jrc $ra699entry:700 %r = ashr i128 %a, %b701 ret i128 %r702}703