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1; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS322; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP643; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM4; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP645; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR66 7; TODO: Test for cvt_w_d is missing, could not generate instruction8 9define double @cvt_d_s(float %a) {10; MIPS32: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_S11; MIPS32FP64: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S12; MM: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_S_MM13; MMFP64: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S_MM14; MMR6: cvt.d.s {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_S_MM15 %1 = fpext float %a to double16 ret double %117}18 19define double @cvt_d_w(i32 %a) {20; MIPS32: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_W21; MIPS32FP64: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W22; MM: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D32_W_MM23; MMFP64: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W_MM24; MMR6: cvt.d.w {{.*}} # <MCInst #{{[0-9]+}} CVT_D64_W_MM25 %1 = sitofp i32 %a to double26 ret double %127}28 29define float @cvt_s_d(double %a) {30; MIPS32: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D3231; MIPS32FP64: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D6432; MM: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D32_MM33; MMFP64: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64_MM34; MMR6: cvt.s.d {{.*}} # <MCInst #{{[0-9]+}} CVT_S_D64_MM35 %1 = fptrunc double %a to float36 ret float %137}38