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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst |\3; RUN: FileCheck %s -check-prefixes=M324; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst |\5; RUN: FileCheck %s -check-prefixes=M326; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst |\7; RUN: FileCheck %s -check-prefixes=M32R2-FP648; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst |\9; RUN: FileCheck %s -check-prefixes=M32R2-SF10; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst |\11; RUN: FileCheck %s -check-prefixes=M32R3R512; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst |\13; RUN: FileCheck %s -check-prefixes=M32R3R514; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst |\15; RUN: FileCheck %s -check-prefixes=M32R616; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst |\17; RUN: FileCheck %s -check-prefixes=M6418; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst |\19; RUN: FileCheck %s -check-prefixes=M6420; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst |\21; RUN: FileCheck %s -check-prefixes=M6422; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst |\23; RUN: FileCheck %s -check-prefixes=M64R624; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst |\25; RUN: FileCheck %s -check-prefixes=MMR2-FP3226; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst |\27; RUN: FileCheck %s -check-prefixes=MMR2-FP6428; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,soft-float -asm-show-inst |\29; RUN: FileCheck %s -check-prefixes=MMR2-SF30; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst |\31; RUN: FileCheck %s -check-prefixes=MMR632; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,soft-float -asm-show-inst |\33; RUN: FileCheck %s -check-prefixes=MMR6-SF34 35; Test that fptosi can be matched for MIPS targets for various FPU36; configurations37 38define i32 @test1(float %t) {39; M32-LABEL: test1:40; M32: # %bb.0: # %entry41; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S42; M32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>43; M32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>44; M32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR45; M32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>46; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC147; M32-NEXT: # <MCOperand Reg:[[#MCREG4:]]>48; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>49;50; M32R2-FP64-LABEL: test1:51; M32R2-FP64: # %bb.0: # %entry52; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S53; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>54; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>55; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR56; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>57; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC158; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>59; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>60;61; M32R2-SF-LABEL: test1:62; M32R2-SF: # %bb.0: # %entry63; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu64; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>65; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>66; M32R2-SF-NEXT: # <MCOperand Imm:-24>>67; M32R2-SF-NEXT: .cfi_def_cfa_offset 2468; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill69; M32R2-SF-NEXT: # <MCInst #[[#MCINST5:]] SW70; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>71; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>72; M32R2-SF-NEXT: # <MCOperand Imm:20>>73; M32R2-SF-NEXT: .cfi_offset 31, -474; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #[[#MCINST6:]] JAL75; M32R2-SF-NEXT: # <MCOperand Expr:__fixsfsi>>76; M32R2-SF-NEXT: nop # <MCInst #[[#MCINST7:]] SLL77; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6:]]>78; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>79; M32R2-SF-NEXT: # <MCOperand Imm:0>>80; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload81; M32R2-SF-NEXT: # <MCInst #[[#MCINST8:]] LW82; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>83; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>84; M32R2-SF-NEXT: # <MCOperand Imm:20>>85; M32R2-SF-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR86; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>87; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu88; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>89; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>90; M32R2-SF-NEXT: # <MCOperand Imm:24>>91;92; M32R3R5-LABEL: test1:93; M32R3R5: # %bb.0: # %entry94; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S95; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1:]]>96; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>97; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR98; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>99; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1100; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG4:]]>101; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>>102;103; M32R6-LABEL: test1:104; M32R6: # %bb.0: # %entry105; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S106; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>107; M32R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>108; M32R6-NEXT: jr $ra # <MCInst #[[#MCINST9:]] JALR109; M32R6-NEXT: # <MCOperand Reg:[[#MCREG6:]]>110; M32R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>111; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1112; M32R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>113; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>114;115; M64-LABEL: test1:116; M64: # %bb.0: # %entry117; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S118; M64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>119; M64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>120; M64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR121; M64-NEXT: # <MCOperand Reg:[[#MCREG7:]]>>122; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1123; M64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>124; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>125;126; M64R6-LABEL: test1:127; M64R6: # %bb.0: # %entry128; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST1:]] TRUNC_W_S129; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>130; M64R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>131; M64R6-NEXT: jr $ra # <MCInst #[[#MCINST10:]] JALR64132; M64R6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>133; M64R6-NEXT: # <MCOperand Reg:[[#MCREG7:]]>>134; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3:]] MFC1135; M64R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>136; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>137;138; MMR2-FP32-LABEL: test1:139; MMR2-FP32: # %bb.0: # %entry140; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST11:]] TRUNC_W_S_MM141; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>142; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>143; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM144; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>145; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM146; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG4:]]>147; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>148;149; MMR2-FP64-LABEL: test1:150; MMR2-FP64: # %bb.0: # %entry151; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST11:]] TRUNC_W_S_MM152; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>153; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>154; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JR_MM155; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>156; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM157; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4:]]>158; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>159;160; MMR2-SF-LABEL: test1:161; MMR2-SF: # %bb.0: # %entry162; MMR2-SF-NEXT: addiusp -24 # <MCInst #[[#MCINST14:]] ADDIUSP_MM163; MMR2-SF-NEXT: # <MCOperand Imm:-24>>164; MMR2-SF-NEXT: .cfi_def_cfa_offset 24165; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill166; MMR2-SF-NEXT: # <MCInst #[[#MCINST15:]] SWSP_MM167; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>168; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>169; MMR2-SF-NEXT: # <MCOperand Imm:20>>170; MMR2-SF-NEXT: .cfi_offset 31, -4171; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #[[#MCINST16:]] JAL_MM172; MMR2-SF-NEXT: # <MCOperand Expr:__fixsfsi>>173; MMR2-SF-NEXT: nop # <MCInst #[[#MCINST17:]] SLL_MM174; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6:]]>175; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>176; MMR2-SF-NEXT: # <MCOperand Imm:0>>177; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload178; MMR2-SF-NEXT: # <MCInst #[[#MCINST18:]] LWSP_MM179; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>180; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>181; MMR2-SF-NEXT: # <MCOperand Imm:20>>182; MMR2-SF-NEXT: addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM183; MMR2-SF-NEXT: # <MCOperand Imm:24>>184; MMR2-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM185; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>186;187; MMR6-LABEL: test1:188; MMR6: # %bb.0: # %entry189; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #[[#MCINST20:]] TRUNC_W_S_MMR6190; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>191; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>192; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13:]] MFC1_MM193; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>194; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>195; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM196; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>>197;198; MMR6-SF-LABEL: test1:199; MMR6-SF: # %bb.0: # %entry200; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4:]] ADDiu201; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5:]]>202; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>203; MMR6-SF-NEXT: # <MCOperand Imm:-24>>204; MMR6-SF-NEXT: .cfi_def_cfa_offset 24205; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill206; MMR6-SF-NEXT: # <MCInst #[[#MCINST5:]] SW207; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3:]]>208; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>209; MMR6-SF-NEXT: # <MCOperand Imm:20>>210; MMR6-SF-NEXT: .cfi_offset 31, -4211; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #[[#MCINST21:]] BALC_MMR6212; MMR6-SF-NEXT: # <MCOperand Expr:__fixsfsi>>213; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload214; MMR6-SF-NEXT: # <MCInst #[[#MCINST8:]] LW215; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>216; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>217; MMR6-SF-NEXT: # <MCOperand Imm:20>>218; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu219; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>220; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>221; MMR6-SF-NEXT: # <MCOperand Imm:24>>222; MMR6-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19:]] JRC16_MM223; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>224entry:225 %conv = fptosi float %t to i32226 ret i32 %conv227}228 229define i32 @test2(double %t) {230; M32-LABEL: test2:231; M32: # %bb.0: # %entry232; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST22:]] TRUNC_W_D32233; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>234; M32-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>235; M32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR236; M32-NEXT: # <MCOperand Reg:[[#MCREG3]]>>237; M32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1238; M32-NEXT: # <MCOperand Reg:[[#MCREG4]]>239; M32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>240;241; M32R2-FP64-LABEL: test2:242; M32R2-FP64: # %bb.0: # %entry243; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64244; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>245; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>246; M32R2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR247; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>>248; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1249; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4]]>250; M32R2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>251;252; M32R2-SF-LABEL: test2:253; M32R2-SF: # %bb.0: # %entry254; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu255; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>256; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>257; M32R2-SF-NEXT: # <MCOperand Imm:-24>>258; M32R2-SF-NEXT: .cfi_def_cfa_offset 24259; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill260; M32R2-SF-NEXT: # <MCInst #[[#MCINST5]] SW261; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>262; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>263; M32R2-SF-NEXT: # <MCOperand Imm:20>>264; M32R2-SF-NEXT: .cfi_offset 31, -4265; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #[[#MCINST6]] JAL266; M32R2-SF-NEXT: # <MCOperand Expr:__fixdfsi>>267; M32R2-SF-NEXT: nop # <MCInst #[[#MCINST7]] SLL268; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>269; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>270; M32R2-SF-NEXT: # <MCOperand Imm:0>>271; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload272; M32R2-SF-NEXT: # <MCInst #[[#MCINST8]] LW273; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>274; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>275; M32R2-SF-NEXT: # <MCOperand Imm:20>>276; M32R2-SF-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR277; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>278; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu279; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>280; M32R2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>281; M32R2-SF-NEXT: # <MCOperand Imm:24>>282;283; M32R3R5-LABEL: test2:284; M32R3R5: # %bb.0: # %entry285; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST22:]] TRUNC_W_D32286; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>287; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>288; M32R3R5-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR289; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG3]]>>290; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1291; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG4]]>292; M32R3R5-NEXT: # <MCOperand Reg:[[#MCREG1]]>>293;294; M32R6-LABEL: test2:295; M32R6: # %bb.0: # %entry296; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64297; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>298; M32R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>299; M32R6-NEXT: jr $ra # <MCInst #[[#MCINST9]] JALR300; M32R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>301; M32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>302; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1303; M32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>304; M32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>305;306; M64-LABEL: test2:307; M64: # %bb.0: # %entry308; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64309; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>310; M64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>311; M64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR312; M64-NEXT: # <MCOperand Reg:[[#MCREG7]]>>313; M64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1314; M64-NEXT: # <MCOperand Reg:[[#MCREG4]]>315; M64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>316;317; M64R6-LABEL: test2:318; M64R6: # %bb.0: # %entry319; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST23:]] TRUNC_W_D64320; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>321; M64R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>322; M64R6-NEXT: jr $ra # <MCInst #[[#MCINST10]] JALR64323; M64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>324; M64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>>325; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST3]] MFC1326; M64R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>327; M64R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>328;329; MMR2-FP32-LABEL: test2:330; MMR2-FP32: # %bb.0: # %entry331; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST24:]] TRUNC_W_MM332; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>333; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG9:]]>>334; MMR2-FP32-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM335; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG3]]>>336; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM337; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG4]]>338; MMR2-FP32-NEXT: # <MCOperand Reg:[[#MCREG1]]>>339;340; MMR2-FP64-LABEL: test2:341; MMR2-FP64: # %bb.0: # %entry342; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #[[#MCINST25:]] CVT_W_D64_MM343; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>344; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>345; MMR2-FP64-NEXT: jr $ra # <MCInst #[[#MCINST12]] JR_MM346; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>>347; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM348; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG4]]>349; MMR2-FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>>350;351; MMR2-SF-LABEL: test2:352; MMR2-SF: # %bb.0: # %entry353; MMR2-SF-NEXT: addiusp -24 # <MCInst #[[#MCINST14]] ADDIUSP_MM354; MMR2-SF-NEXT: # <MCOperand Imm:-24>>355; MMR2-SF-NEXT: .cfi_def_cfa_offset 24356; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill357; MMR2-SF-NEXT: # <MCInst #[[#MCINST15]] SWSP_MM358; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>359; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>360; MMR2-SF-NEXT: # <MCOperand Imm:20>>361; MMR2-SF-NEXT: .cfi_offset 31, -4362; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #[[#MCINST16]] JAL_MM363; MMR2-SF-NEXT: # <MCOperand Expr:__fixdfsi>>364; MMR2-SF-NEXT: nop # <MCInst #[[#MCINST17]] SLL_MM365; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>366; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG6]]>367; MMR2-SF-NEXT: # <MCOperand Imm:0>>368; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload369; MMR2-SF-NEXT: # <MCInst #[[#MCINST18]] LWSP_MM370; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>371; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>372; MMR2-SF-NEXT: # <MCOperand Imm:20>>373; MMR2-SF-NEXT: addiusp 24 # <MCInst #[[#MCINST14]] ADDIUSP_MM374; MMR2-SF-NEXT: # <MCOperand Imm:24>>375; MMR2-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM376; MMR2-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>377;378; MMR6-LABEL: test2:379; MMR6: # %bb.0: # %entry380; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #[[#MCINST26:]] TRUNC_W_D_MMR6381; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>382; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>>383; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #[[#MCINST13]] MFC1_MM384; MMR6-NEXT: # <MCOperand Reg:[[#MCREG4]]>385; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>>386; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM387; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>>388;389; MMR6-SF-LABEL: test2:390; MMR6-SF: # %bb.0: # %entry391; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #[[#MCINST4]] ADDiu392; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>393; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>394; MMR6-SF-NEXT: # <MCOperand Imm:-24>>395; MMR6-SF-NEXT: .cfi_def_cfa_offset 24396; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill397; MMR6-SF-NEXT: # <MCInst #[[#MCINST5]] SW398; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>399; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>400; MMR6-SF-NEXT: # <MCOperand Imm:20>>401; MMR6-SF-NEXT: .cfi_offset 31, -4402; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #[[#MCINST21]] BALC_MMR6403; MMR6-SF-NEXT: # <MCOperand Expr:__fixdfsi>>404; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload405; MMR6-SF-NEXT: # <MCInst #[[#MCINST8]] LW406; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>407; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>408; MMR6-SF-NEXT: # <MCOperand Imm:20>>409; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #[[#MCINST4]] ADDiu410; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>411; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG5]]>412; MMR6-SF-NEXT: # <MCOperand Imm:24>>413; MMR6-SF-NEXT: jrc $ra # <MCInst #[[#MCINST19]] JRC16_MM414; MMR6-SF-NEXT: # <MCOperand Reg:[[#MCREG3]]>>415entry:416 %conv = fptosi double %t to i32417 ret i32 %conv418}419