1540 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS323; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR34; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R65; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR66; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips3 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS37; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS648; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R69; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips,+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MMR5FP6410; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r5 -mattr=+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R5FP64311 12; Test subword and word loads. We use -asm-show-inst to test that the produced13; instructions match the expected ISA.14 15; NOTE: As the -asm-show-inst shows the internal numbering of instructions16; and registers, these numbers have been replaced with wildcard regexes.17 18@a = common global i8 0, align 419@b = common global i16 0, align 420@c = common global i32 0, align 421@d = common global i64 0, align 822@e = common global float 0.0, align 423@f = common global double 0.0, align 824 25define i8 @f1() {26; MIPS32-LABEL: f1:27; MIPS32: # %bb.0: # %entry28; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi29; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>30; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,a)>>31; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR32; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>33; MIPS32-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu34; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>35; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>36; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,a)>>37;38; MMR3-LABEL: f1:39; MMR3: # %bb.0: # %entry40; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM41; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1:]]>42; MMR3-NEXT: # <MCOperand Expr:specifier(4024,a)>>43; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM44; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>45; MMR3-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM46; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3:]]>47; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>48; MMR3-NEXT: # <MCOperand Expr:specifier(4027,a)>>49;50; MIPS32R6-LABEL: f1:51; MIPS32R6: # %bb.0: # %entry52; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi53; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>54; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,a)>>55; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7:]] JALR56; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>57; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>58; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu59; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>60; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>61; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,a)>>62;63; MMR6-LABEL: f1:64; MMR6: # %bb.0: # %entry65; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM66; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>67; MMR6-NEXT: # <MCOperand Expr:specifier(4024,a)>>68; MMR6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM69; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>70; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>71; MMR6-NEXT: # <MCOperand Expr:specifier(4027,a)>>72; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM73; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>74;75; MIPS3-LABEL: f1:76; MIPS3: # %bb.0: # %entry77; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi6478; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5:]]>79; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,a)>>80; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu81; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>82; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>83; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,a)>>84; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL85; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>86; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>87; MIPS3-NEXT: # <MCOperand Imm:16>>88; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu89; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>90; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>91; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,a)>>92; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL93; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>94; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>95; MIPS3-NEXT: # <MCOperand Imm:16>>96; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR97; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>98; MIPS3-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu99; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3:]]>100; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>101; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,a)>>102;103; MIPS64-LABEL: f1:104; MIPS64: # %bb.0: # %entry105; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64106; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5:]]>107; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,a)>>108; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu109; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>110; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>111; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,a)>>112; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL113; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>114; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>115; MIPS64-NEXT: # <MCOperand Imm:16>>116; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu117; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>118; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>119; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,a)>>120; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL121; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>122; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>123; MIPS64-NEXT: # <MCOperand Imm:16>>124; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR125; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>126; MIPS64-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu127; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>128; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>129; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,a)>>130;131; MIPS64R6-LABEL: f1:132; MIPS64R6: # %bb.0: # %entry133; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64134; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5:]]>135; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,a)>>136; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu137; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>138; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>139; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,a)>>140; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL141; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>142; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>143; MIPS64R6-NEXT: # <MCOperand Imm:16>>144; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu145; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>146; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>147; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,a)>>148; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL149; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>150; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>151; MIPS64R6-NEXT: # <MCOperand Imm:16>>152; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12:]] JALR64153; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7:]]>154; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>155; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu156; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>157; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>158; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,a)>>159;160; MMR5FP64-LABEL: f1:161; MMR5FP64: # %bb.0: # %entry162; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM163; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>164; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,a)>>165; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM166; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>167; MMR5FP64-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST6:]] LBu_MM168; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>169; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>170; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,a)>>171;172; MIPS32R5FP643-LABEL: f1:173; MIPS32R5FP643: # %bb.0: # %entry174; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi175; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1:]]>176; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,a)>>177; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR178; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>179; MIPS32R5FP643-NEXT: lbu $2, %lo(a)($1) # <MCInst #[[#MCINST3:]] LBu180; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3:]]>181; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>182; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,a)>>183entry:184 %0 = load i8, ptr @a185 ret i8 %0186}187 188define i32 @f2() {189; MIPS32-LABEL: f2:190; MIPS32: # %bb.0: # %entry191; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi192; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>193; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,a)>>194; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR195; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>196; MIPS32-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB197; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>198; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>199; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,a)>>200;201; MMR3-LABEL: f2:202; MMR3: # %bb.0: # %entry203; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM204; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>205; MMR3-NEXT: # <MCOperand Expr:specifier(4024,a)>>206; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM207; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>208; MMR3-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB_MM209; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>210; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>211; MMR3-NEXT: # <MCOperand Expr:specifier(4027,a)>>212;213; MIPS32R6-LABEL: f2:214; MIPS32R6: # %bb.0: # %entry215; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi216; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>217; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,a)>>218; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR219; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>220; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>221; MIPS32R6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB222; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>223; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>224; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,a)>>225;226; MMR6-LABEL: f2:227; MMR6: # %bb.0: # %entry228; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM229; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>230; MMR6-NEXT: # <MCOperand Expr:specifier(4024,a)>>231; MMR6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB_MM232; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>233; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>234; MMR6-NEXT: # <MCOperand Expr:specifier(4027,a)>>235; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM236; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>237;238; MIPS3-LABEL: f2:239; MIPS3: # %bb.0: # %entry240; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64241; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>242; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,a)>>243; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu244; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>245; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>246; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,a)>>247; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL248; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>249; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>250; MIPS3-NEXT: # <MCOperand Imm:16>>251; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu252; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>253; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>254; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,a)>>255; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL256; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>257; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>258; MIPS3-NEXT: # <MCOperand Imm:16>>259; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR260; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>261; MIPS3-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB262; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3]]>263; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>264; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,a)>>265;266; MIPS64-LABEL: f2:267; MIPS64: # %bb.0: # %entry268; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64269; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>270; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,a)>>271; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu272; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>273; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>274; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,a)>>275; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL276; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>277; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>278; MIPS64-NEXT: # <MCOperand Imm:16>>279; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu280; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>281; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>282; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,a)>>283; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL284; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>285; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>286; MIPS64-NEXT: # <MCOperand Imm:16>>287; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR288; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>289; MIPS64-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB290; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3]]>291; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>292; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,a)>>293;294; MIPS64R6-LABEL: f2:295; MIPS64R6: # %bb.0: # %entry296; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9]] LUi64297; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>298; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,a)>>299; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10]] DADDiu300; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>301; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>302; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,a)>>303; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL304; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>305; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>306; MIPS64R6-NEXT: # <MCOperand Imm:16>>307; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu308; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>309; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>310; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,a)>>311; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL312; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>313; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>314; MIPS64R6-NEXT: # <MCOperand Imm:16>>315; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64316; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>317; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>318; MIPS64R6-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB319; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>320; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>321; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,a)>>322;323; MMR5FP64-LABEL: f2:324; MMR5FP64: # %bb.0: # %entry325; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4]] LUi_MM326; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>327; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,a)>>328; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM329; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>330; MMR5FP64-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST14:]] LB_MM331; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>332; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>333; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,a)>>334;335; MIPS32R5FP643-LABEL: f2:336; MIPS32R5FP643: # %bb.0: # %entry337; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1]] LUi338; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>339; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,a)>>340; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR341; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>342; MIPS32R5FP643-NEXT: lb $2, %lo(a)($1) # <MCInst #[[#MCINST13:]] LB343; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>344; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>345; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,a)>>346entry:347 %0 = load i8, ptr @a348 %1 = sext i8 %0 to i32349 ret i32 %1350}351 352define i16 @f3() {353; MIPS32-LABEL: f3:354; MIPS32: # %bb.0: # %entry355; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi356; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>357; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,b)>>358; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR359; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>360; MIPS32-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu361; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>362; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>363; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,b)>>364;365; MMR3-LABEL: f3:366; MMR3: # %bb.0: # %entry367; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM368; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>369; MMR3-NEXT: # <MCOperand Expr:specifier(4024,b)>>370; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM371; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>372; MMR3-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu_MM373; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>374; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>375; MMR3-NEXT: # <MCOperand Expr:specifier(4027,b)>>376;377; MIPS32R6-LABEL: f3:378; MIPS32R6: # %bb.0: # %entry379; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi380; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>381; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,b)>>382; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR383; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>384; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>385; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu386; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>387; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>388; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,b)>>389;390; MMR6-LABEL: f3:391; MMR6: # %bb.0: # %entry392; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM393; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>394; MMR6-NEXT: # <MCOperand Expr:specifier(4024,b)>>395; MMR6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu_MM396; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>397; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>398; MMR6-NEXT: # <MCOperand Expr:specifier(4027,b)>>399; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM400; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>401;402; MIPS3-LABEL: f3:403; MIPS3: # %bb.0: # %entry404; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64405; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>406; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,b)>>407; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu408; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>409; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>410; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,b)>>411; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL412; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>413; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>414; MIPS3-NEXT: # <MCOperand Imm:16>>415; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu416; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>417; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>418; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,b)>>419; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL420; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>421; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>422; MIPS3-NEXT: # <MCOperand Imm:16>>423; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR424; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>425; MIPS3-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu426; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3]]>427; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>428; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,b)>>429;430; MIPS64-LABEL: f3:431; MIPS64: # %bb.0: # %entry432; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64433; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>434; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,b)>>435; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu436; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>437; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>438; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,b)>>439; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL440; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>441; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>442; MIPS64-NEXT: # <MCOperand Imm:16>>443; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu444; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>445; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>446; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,b)>>447; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL448; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>449; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>450; MIPS64-NEXT: # <MCOperand Imm:16>>451; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR452; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>453; MIPS64-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu454; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3]]>455; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>456; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,b)>>457;458; MIPS64R6-LABEL: f3:459; MIPS64R6: # %bb.0: # %entry460; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64461; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>462; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,b)>>463; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu464; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>465; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>466; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,b)>>467; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL468; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>469; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>470; MIPS64R6-NEXT: # <MCOperand Imm:16>>471; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu472; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>473; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>474; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,b)>>475; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL476; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>477; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>478; MIPS64R6-NEXT: # <MCOperand Imm:16>>479; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64480; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>481; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>482; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu483; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>484; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>485; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,b)>>486;487; MMR5FP64-LABEL: f3:488; MMR5FP64: # %bb.0: # %entry489; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM490; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>491; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,b)>>492; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM493; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>494; MMR5FP64-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST16:]] LHu_MM495; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>496; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>497; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,b)>>498;499; MIPS32R5FP643-LABEL: f3:500; MIPS32R5FP643: # %bb.0: # %entry501; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi502; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>503; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,b)>>504; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR505; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>506; MIPS32R5FP643-NEXT: lhu $2, %lo(b)($1) # <MCInst #[[#MCINST15:]] LHu507; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>508; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>509; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,b)>>510entry:511 %0 = load i16, ptr @b512 ret i16 %0513}514 515define i32 @f4() {516; MIPS32-LABEL: f4:517; MIPS32: # %bb.0: # %entry518; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi519; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>520; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,b)>>521; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR522; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>523; MIPS32-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH524; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>525; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>526; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,b)>>527;528; MMR3-LABEL: f4:529; MMR3: # %bb.0: # %entry530; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM531; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>532; MMR3-NEXT: # <MCOperand Expr:specifier(4024,b)>>533; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM534; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>535; MMR3-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH_MM536; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>537; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>538; MMR3-NEXT: # <MCOperand Expr:specifier(4027,b)>>539;540; MIPS32R6-LABEL: f4:541; MIPS32R6: # %bb.0: # %entry542; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi543; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>544; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,b)>>545; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR546; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>547; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>548; MIPS32R6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH549; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>550; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>551; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,b)>>552;553; MMR6-LABEL: f4:554; MMR6: # %bb.0: # %entry555; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM556; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>557; MMR6-NEXT: # <MCOperand Expr:specifier(4024,b)>>558; MMR6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH_MM559; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>560; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>561; MMR6-NEXT: # <MCOperand Expr:specifier(4027,b)>>562; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM563; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>564;565; MIPS3-LABEL: f4:566; MIPS3: # %bb.0: # %entry567; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64568; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>569; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,b)>>570; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu571; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>572; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>573; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,b)>>574; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL575; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>576; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>577; MIPS3-NEXT: # <MCOperand Imm:16>>578; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu579; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>580; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>581; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,b)>>582; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL583; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>584; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>585; MIPS3-NEXT: # <MCOperand Imm:16>>586; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR587; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>588; MIPS3-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH589; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3]]>590; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>591; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,b)>>592;593; MIPS64-LABEL: f4:594; MIPS64: # %bb.0: # %entry595; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64596; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>597; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,b)>>598; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu599; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>600; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>601; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,b)>>602; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL603; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>604; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>605; MIPS64-NEXT: # <MCOperand Imm:16>>606; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu607; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>608; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>609; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,b)>>610; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL611; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>612; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>613; MIPS64-NEXT: # <MCOperand Imm:16>>614; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR615; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>616; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH617; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3]]>618; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>619; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,b)>>620;621; MIPS64R6-LABEL: f4:622; MIPS64R6: # %bb.0: # %entry623; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64624; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>625; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,b)>>626; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu627; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>628; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>629; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,b)>>630; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL631; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>632; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>633; MIPS64R6-NEXT: # <MCOperand Imm:16>>634; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu635; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>636; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>637; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,b)>>638; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL639; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>640; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>641; MIPS64R6-NEXT: # <MCOperand Imm:16>>642; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64643; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>644; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>645; MIPS64R6-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH646; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>647; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>648; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,b)>>649;650; MMR5FP64-LABEL: f4:651; MMR5FP64: # %bb.0: # %entry652; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM653; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>654; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,b)>>655; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM656; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>657; MMR5FP64-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST18:]] LH_MM658; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>659; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>660; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,b)>>661;662; MIPS32R5FP643-LABEL: f4:663; MIPS32R5FP643: # %bb.0: # %entry664; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi665; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>666; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,b)>>667; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR668; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>669; MIPS32R5FP643-NEXT: lh $2, %lo(b)($1) # <MCInst #[[#MCINST17:]] LH670; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>671; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>672; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,b)>>673entry:674 %0 = load i16, ptr @b675 %1 = sext i16 %0 to i32676 ret i32 %1677}678 679define i32 @f5() {680; MIPS32-LABEL: f5:681; MIPS32: # %bb.0: # %entry682; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi683; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>684; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,c)>>685; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR686; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>687; MIPS32-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW688; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>689; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>690; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,c)>>691;692; MMR3-LABEL: f5:693; MMR3: # %bb.0: # %entry694; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM695; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>696; MMR3-NEXT: # <MCOperand Expr:specifier(4024,c)>>697; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM698; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>699; MMR3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW_MM700; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>701; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>702; MMR3-NEXT: # <MCOperand Expr:specifier(4027,c)>>703;704; MIPS32R6-LABEL: f5:705; MIPS32R6: # %bb.0: # %entry706; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi707; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>708; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,c)>>709; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR710; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>711; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>712; MIPS32R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW713; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>714; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>715; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,c)>>716;717; MMR6-LABEL: f5:718; MMR6: # %bb.0: # %entry719; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM720; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>721; MMR6-NEXT: # <MCOperand Expr:specifier(4024,c)>>722; MMR6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW_MM723; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>724; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>725; MMR6-NEXT: # <MCOperand Expr:specifier(4027,c)>>726; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM727; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>728;729; MIPS3-LABEL: f5:730; MIPS3: # %bb.0: # %entry731; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64732; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>733; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,c)>>734; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu735; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>736; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>737; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,c)>>738; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL739; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>740; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>741; MIPS3-NEXT: # <MCOperand Imm:16>>742; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu743; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>744; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>745; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,c)>>746; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL747; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>748; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>749; MIPS3-NEXT: # <MCOperand Imm:16>>750; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR751; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>752; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW753; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG3]]>754; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>755; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,c)>>756;757; MIPS64-LABEL: f5:758; MIPS64: # %bb.0: # %entry759; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64760; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>761; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,c)>>762; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu763; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>764; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>765; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,c)>>766; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL767; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>768; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>769; MIPS64-NEXT: # <MCOperand Imm:16>>770; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu771; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>772; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>773; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,c)>>774; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL775; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>776; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>777; MIPS64-NEXT: # <MCOperand Imm:16>>778; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR779; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>780; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW781; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG3]]>782; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>783; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,c)>>784;785; MIPS64R6-LABEL: f5:786; MIPS64R6: # %bb.0: # %entry787; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64788; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>789; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,c)>>790; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu791; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>792; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>793; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,c)>>794; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL795; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>796; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>797; MIPS64R6-NEXT: # <MCOperand Imm:16>>798; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu799; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>800; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>801; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,c)>>802; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL803; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>804; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>805; MIPS64R6-NEXT: # <MCOperand Imm:16>>806; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64807; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>808; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>809; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW810; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>811; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>812; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,c)>>813;814; MMR5FP64-LABEL: f5:815; MMR5FP64: # %bb.0: # %entry816; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM817; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>818; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,c)>>819; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM820; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>821; MMR5FP64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST20:]] LW_MM822; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>823; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>824; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,c)>>825;826; MIPS32R5FP643-LABEL: f5:827; MIPS32R5FP643: # %bb.0: # %entry828; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi829; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>830; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,c)>>831; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR832; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>833; MIPS32R5FP643-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST19:]] LW834; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>835; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>836; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,c)>>837entry:838 %0 = load i32, ptr @c839 ret i32 %0840}841 842define i64 @f6() {843; MIPS32-LABEL: f6:844; MIPS32: # %bb.0: # %entry845; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi846; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>847; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,c)>>848; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW849; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG8:]]>850; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>851; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,c)>>852; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR853; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>854; MIPS32-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST21:]] ADDiu855; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>856; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG4:]]>857; MIPS32-NEXT: # <MCOperand Imm:0>>858;859; MMR3-LABEL: f6:860; MMR3: # %bb.0: # %entry861; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM862; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>863; MMR3-NEXT: # <MCOperand Expr:specifier(4024,c)>>864; MMR3-NEXT: li16 $2, 0 # <MCInst #[[#MCINST22:]] LI16_MM865; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>866; MMR3-NEXT: # <MCOperand Imm:0>>867; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM868; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>869; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM870; MMR3-NEXT: # <MCOperand Reg:[[#MCREG8:]]>871; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>872; MMR3-NEXT: # <MCOperand Expr:specifier(4027,c)>>873;874; MIPS32R6-LABEL: f6:875; MIPS32R6: # %bb.0: # %entry876; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi877; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>878; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,c)>>879; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW880; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>881; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>882; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,c)>>883; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR884; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>885; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>886; MIPS32R6-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST21:]] ADDiu887; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>888; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>889; MIPS32R6-NEXT: # <MCOperand Imm:0>>890;891; MMR6-LABEL: f6:892; MMR6: # %bb.0: # %entry893; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM894; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>895; MMR6-NEXT: # <MCOperand Expr:specifier(4024,c)>>896; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM897; MMR6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>898; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>899; MMR6-NEXT: # <MCOperand Expr:specifier(4027,c)>>900; MMR6-NEXT: li16 $2, 0 # <MCInst #[[#MCINST22:]] LI16_MM901; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>902; MMR6-NEXT: # <MCOperand Imm:0>>903; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM904; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>905;906; MIPS3-LABEL: f6:907; MIPS3: # %bb.0: # %entry908; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64909; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>910; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,c)>>911; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu912; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>913; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>914; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,c)>>915; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL916; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>917; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>918; MIPS3-NEXT: # <MCOperand Imm:16>>919; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu920; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>921; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>922; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,c)>>923; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL924; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>925; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>926; MIPS3-NEXT: # <MCOperand Imm:16>>927; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR928; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>929; MIPS3-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST23:]] LWu930; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG9:]]>931; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>932; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,c)>>933;934; MIPS64-LABEL: f6:935; MIPS64: # %bb.0: # %entry936; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64937; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>938; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,c)>>939; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu940; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>941; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>942; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,c)>>943; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL944; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>945; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>946; MIPS64-NEXT: # <MCOperand Imm:16>>947; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu948; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>949; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>950; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,c)>>951; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL952; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>953; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>954; MIPS64-NEXT: # <MCOperand Imm:16>>955; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR956; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>957; MIPS64-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST23:]] LWu958; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG9:]]>959; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>960; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,c)>>961;962; MIPS64R6-LABEL: f6:963; MIPS64R6: # %bb.0: # %entry964; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64965; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>966; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,c)>>967; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu968; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>969; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>970; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,c)>>971; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL972; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>973; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>974; MIPS64R6-NEXT: # <MCOperand Imm:16>>975; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu976; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>977; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>978; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,c)>>979; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL980; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>981; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>982; MIPS64R6-NEXT: # <MCOperand Imm:16>>983; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR64984; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>985; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>986; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # <MCInst #[[#MCINST23:]] LWu987; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG9:]]>988; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>989; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,c)>>990;991; MMR5FP64-LABEL: f6:992; MMR5FP64: # %bb.0: # %entry993; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM994; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>995; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,c)>>996; MMR5FP64-NEXT: li16 $2, 0 # <MCInst #[[#MCINST22:]] LI16_MM997; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>998; MMR5FP64-NEXT: # <MCOperand Imm:0>>999; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM1000; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1001; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM1002; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG8:]]>1003; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>1004; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,c)>>1005;1006; MIPS32R5FP643-LABEL: f6:1007; MIPS32R5FP643: # %bb.0: # %entry1008; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi1009; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>1010; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,c)>>1011; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW1012; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG8:]]>1013; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>1014; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,c)>>1015; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1016; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1017; MIPS32R5FP643-NEXT: addiu $2, $zero, 0 # <MCInst #[[#MCINST21:]] ADDiu1018; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>1019; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG4:]]>1020; MIPS32R5FP643-NEXT: # <MCOperand Imm:0>>1021entry:1022 %0 = load i32, ptr @c1023 %1 = zext i32 %0 to i641024 ret i64 %11025}1026 1027define i64 @f7() {1028; MIPS32-LABEL: f7:1029; MIPS32: # %bb.0: # %entry1030; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi1031; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>1032; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,c)>>1033; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW1034; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG8]]>1035; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>1036; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,c)>>1037; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1038; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1039; MIPS32-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST24:]] SRA1040; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>1041; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG8]]>1042; MIPS32-NEXT: # <MCOperand Imm:31>>1043;1044; MMR3-LABEL: f7:1045; MMR3: # %bb.0: # %entry1046; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM1047; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>1048; MMR3-NEXT: # <MCOperand Expr:specifier(4024,c)>>1049; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM1050; MMR3-NEXT: # <MCOperand Reg:[[#MCREG8]]>1051; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>1052; MMR3-NEXT: # <MCOperand Expr:specifier(4027,c)>>1053; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM1054; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1055; MMR3-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA_MM1056; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>1057; MMR3-NEXT: # <MCOperand Reg:[[#MCREG8]]>1058; MMR3-NEXT: # <MCOperand Imm:31>>1059;1060; MIPS32R6-LABEL: f7:1061; MIPS32R6: # %bb.0: # %entry1062; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi1063; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1064; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,c)>>1065; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW1066; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>1067; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1068; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,c)>>1069; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR1070; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>1071; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1072; MIPS32R6-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST24:]] SRA1073; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>1074; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>1075; MIPS32R6-NEXT: # <MCOperand Imm:31>>1076;1077; MMR6-LABEL: f7:1078; MMR6: # %bb.0: # %entry1079; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM1080; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1081; MMR6-NEXT: # <MCOperand Expr:specifier(4024,c)>>1082; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM1083; MMR6-NEXT: # <MCOperand Reg:[[#MCREG8]]>1084; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1085; MMR6-NEXT: # <MCOperand Expr:specifier(4027,c)>>1086; MMR6-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA_MM1087; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>1088; MMR6-NEXT: # <MCOperand Reg:[[#MCREG8]]>1089; MMR6-NEXT: # <MCOperand Imm:31>>1090; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM1091; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1092;1093; MIPS3-LABEL: f7:1094; MIPS3: # %bb.0: # %entry1095; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi641096; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1097; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,c)>>1098; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu1099; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1100; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1101; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,c)>>1102; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1103; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1104; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1105; MIPS3-NEXT: # <MCOperand Imm:16>>1106; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu1107; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1108; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1109; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,c)>>1110; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1111; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1112; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1113; MIPS3-NEXT: # <MCOperand Imm:16>>1114; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1115; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1116; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST26:]] LW641117; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG9]]>1118; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1119; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,c)>>1120;1121; MIPS64-LABEL: f7:1122; MIPS64: # %bb.0: # %entry1123; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi641124; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1125; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,c)>>1126; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu1127; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1128; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1129; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,c)>>1130; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1131; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1132; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1133; MIPS64-NEXT: # <MCOperand Imm:16>>1134; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu1135; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1136; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1137; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,c)>>1138; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1139; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1140; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1141; MIPS64-NEXT: # <MCOperand Imm:16>>1142; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1143; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1144; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST26:]] LW641145; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG9]]>1146; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1147; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,c)>>1148;1149; MIPS64R6-LABEL: f7:1150; MIPS64R6: # %bb.0: # %entry1151; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi641152; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1153; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,c)>>1154; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu1155; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1156; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1157; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,c)>>1158; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1159; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1160; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1161; MIPS64R6-NEXT: # <MCOperand Imm:16>>1162; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu1163; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1164; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1165; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,c)>>1166; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1167; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1168; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1169; MIPS64R6-NEXT: # <MCOperand Imm:16>>1170; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR641171; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>1172; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1173; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #[[#MCINST26:]] LW641174; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG9]]>1175; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1176; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,c)>>1177;1178; MMR5FP64-LABEL: f7:1179; MMR5FP64: # %bb.0: # %entry1180; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM1181; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>1182; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,c)>>1183; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST20]] LW_MM1184; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG8]]>1185; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>1186; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,c)>>1187; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM1188; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1189; MMR5FP64-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST25:]] SRA_MM1190; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>1191; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG8]]>1192; MMR5FP64-NEXT: # <MCOperand Imm:31>>1193;1194; MIPS32R5FP643-LABEL: f7:1195; MIPS32R5FP643: # %bb.0: # %entry1196; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi1197; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>1198; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,c)>>1199; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #[[#MCINST19]] LW1200; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG8]]>1201; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>1202; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,c)>>1203; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1204; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1205; MIPS32R5FP643-NEXT: sra $2, $3, 31 # <MCInst #[[#MCINST24:]] SRA1206; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>1207; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG8]]>1208; MIPS32R5FP643-NEXT: # <MCOperand Imm:31>>1209entry:1210 %0 = load i32, ptr @c1211 %1 = sext i32 %0 to i641212 ret i64 %11213}1214 1215define float @f8() {1216; MIPS32-LABEL: f8:1217; MIPS32: # %bb.0: # %entry1218; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi1219; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>1220; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,e)>>1221; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1222; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1223; MIPS32-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC11224; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1225; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>1226; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,e)>>1227;1228; MMR3-LABEL: f8:1229; MMR3: # %bb.0: # %entry1230; MMR3-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM1231; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>1232; MMR3-NEXT: # <MCOperand Expr:specifier(4024,e)>>1233; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM1234; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1235; MMR3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1_MM1236; MMR3-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1237; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>1238; MMR3-NEXT: # <MCOperand Expr:specifier(4027,e)>>1239;1240; MIPS32R6-LABEL: f8:1241; MIPS32R6: # %bb.0: # %entry1242; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi1243; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1244; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,e)>>1245; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR1246; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>1247; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1248; MIPS32R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC11249; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1250; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1251; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,e)>>1252;1253; MMR6-LABEL: f8:1254; MMR6: # %bb.0: # %entry1255; MMR6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM1256; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1257; MMR6-NEXT: # <MCOperand Expr:specifier(4024,e)>>1258; MMR6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1_MM1259; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1260; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1261; MMR6-NEXT: # <MCOperand Expr:specifier(4027,e)>>1262; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM1263; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1264;1265; MIPS3-LABEL: f8:1266; MIPS3: # %bb.0: # %entry1267; MIPS3-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi641268; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1269; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,e)>>1270; MIPS3-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu1271; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1272; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1273; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,e)>>1274; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1275; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1276; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1277; MIPS3-NEXT: # <MCOperand Imm:16>>1278; MIPS3-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu1279; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1280; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1281; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,e)>>1282; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1283; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1284; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1285; MIPS3-NEXT: # <MCOperand Imm:16>>1286; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1287; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1288; MIPS3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC11289; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1290; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1291; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,e)>>1292;1293; MIPS64-LABEL: f8:1294; MIPS64: # %bb.0: # %entry1295; MIPS64-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi641296; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1297; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,e)>>1298; MIPS64-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu1299; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1300; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1301; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,e)>>1302; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1303; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1304; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1305; MIPS64-NEXT: # <MCOperand Imm:16>>1306; MIPS64-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu1307; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1308; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1309; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,e)>>1310; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1311; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1312; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1313; MIPS64-NEXT: # <MCOperand Imm:16>>1314; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1315; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1316; MIPS64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC11317; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1318; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1319; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,e)>>1320;1321; MIPS64R6-LABEL: f8:1322; MIPS64R6: # %bb.0: # %entry1323; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi641324; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1325; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,e)>>1326; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu1327; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1328; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1329; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,e)>>1330; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1331; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1332; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1333; MIPS64R6-NEXT: # <MCOperand Imm:16>>1334; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu1335; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1336; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1337; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,e)>>1338; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1339; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1340; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1341; MIPS64R6-NEXT: # <MCOperand Imm:16>>1342; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR641343; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>1344; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1345; MIPS64R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC11346; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1347; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1348; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,e)>>1349;1350; MMR5FP64-LABEL: f8:1351; MMR5FP64: # %bb.0: # %entry1352; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM1353; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>1354; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,e)>>1355; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM1356; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1357; MMR5FP64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST28:]] LWC1_MM1358; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1359; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>1360; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,e)>>1361;1362; MIPS32R5FP643-LABEL: f8:1363; MIPS32R5FP643: # %bb.0: # %entry1364; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi1365; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>1366; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,e)>>1367; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1368; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1369; MIPS32R5FP643-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #[[#MCINST27:]] LWC11370; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG10:]]>1371; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>1372; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,e)>>1373entry:1374 %0 = load float, ptr @e1375 ret float %01376}1377 1378define double @f9() {1379; MIPS32-LABEL: f9:1380; MIPS32: # %bb.0: # %entry1381; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi1382; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>1383; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,f)>>1384; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1385; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1386; MIPS32-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST29:]] LDC11387; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG11:]]>1388; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>1389; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,f)>>1390;1391; MMR3-LABEL: f9:1392; MMR3: # %bb.0: # %entry1393; MMR3-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM1394; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>1395; MMR3-NEXT: # <MCOperand Expr:specifier(4024,f)>>1396; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM1397; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1398; MMR3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST30:]] LDC1_MM_D321399; MMR3-NEXT: # <MCOperand Reg:[[#MCREG11:]]>1400; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>1401; MMR3-NEXT: # <MCOperand Expr:specifier(4027,f)>>1402;1403; MIPS32R6-LABEL: f9:1404; MIPS32R6: # %bb.0: # %entry1405; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi1406; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1407; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,f)>>1408; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR1409; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>1410; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1411; MIPS32R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC1641412; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG12:]]>1413; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1414; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,f)>>1415;1416; MMR6-LABEL: f9:1417; MMR6: # %bb.0: # %entry1418; MMR6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM1419; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1420; MMR6-NEXT: # <MCOperand Expr:specifier(4024,f)>>1421; MMR6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST32:]] LDC1_D64_MMR61422; MMR6-NEXT: # <MCOperand Reg:[[#MCREG12:]]>1423; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>1424; MMR6-NEXT: # <MCOperand Expr:specifier(4027,f)>>1425; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM1426; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1427;1428; MIPS3-LABEL: f9:1429; MIPS3: # %bb.0: # %entry1430; MIPS3-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi641431; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1432; MIPS3-NEXT: # <MCOperand Expr:specifier(4026,f)>>1433; MIPS3-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu1434; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1435; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1436; MIPS3-NEXT: # <MCOperand Expr:specifier(4025,f)>>1437; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1438; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1439; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1440; MIPS3-NEXT: # <MCOperand Imm:16>>1441; MIPS3-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu1442; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1443; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1444; MIPS3-NEXT: # <MCOperand Expr:specifier(4024,f)>>1445; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1446; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1447; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1448; MIPS3-NEXT: # <MCOperand Imm:16>>1449; MIPS3-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1450; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1451; MIPS3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC1641452; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG12:]]>1453; MIPS3-NEXT: # <MCOperand Reg:[[#MCREG5]]>1454; MIPS3-NEXT: # <MCOperand Expr:specifier(4027,f)>>1455;1456; MIPS64-LABEL: f9:1457; MIPS64: # %bb.0: # %entry1458; MIPS64-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi641459; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1460; MIPS64-NEXT: # <MCOperand Expr:specifier(4026,f)>>1461; MIPS64-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu1462; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1463; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1464; MIPS64-NEXT: # <MCOperand Expr:specifier(4025,f)>>1465; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1466; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1467; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1468; MIPS64-NEXT: # <MCOperand Imm:16>>1469; MIPS64-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu1470; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1471; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1472; MIPS64-NEXT: # <MCOperand Expr:specifier(4024,f)>>1473; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1474; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1475; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1476; MIPS64-NEXT: # <MCOperand Imm:16>>1477; MIPS64-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1478; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1479; MIPS64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC1641480; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG12:]]>1481; MIPS64-NEXT: # <MCOperand Reg:[[#MCREG5]]>1482; MIPS64-NEXT: # <MCOperand Expr:specifier(4027,f)>>1483;1484; MIPS64R6-LABEL: f9:1485; MIPS64R6: # %bb.0: # %entry1486; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi641487; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1488; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,f)>>1489; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu1490; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1491; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1492; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,f)>>1493; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1494; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1495; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1496; MIPS64R6-NEXT: # <MCOperand Imm:16>>1497; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu1498; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1499; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1500; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,f)>>1501; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL1502; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1503; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1504; MIPS64R6-NEXT: # <MCOperand Imm:16>>1505; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST12]] JALR641506; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>1507; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>1508; MIPS64R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC1641509; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG12:]]>1510; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>1511; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,f)>>1512;1513; MMR5FP64-LABEL: f9:1514; MMR5FP64: # %bb.0: # %entry1515; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM1516; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>1517; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,f)>>1518; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM1519; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1520; MMR5FP64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST33:]] LDC1_MM_D641521; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG12:]]>1522; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>1523; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,f)>>1524;1525; MIPS32R5FP643-LABEL: f9:1526; MIPS32R5FP643: # %bb.0: # %entry1527; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi1528; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>1529; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,f)>>1530; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR1531; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>1532; MIPS32R5FP643-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #[[#MCINST31:]] LDC1641533; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG12:]]>1534; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>1535; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,f)>>1536entry:1537 %0 = load double, ptr @f1538 ret double %01539}1540