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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \3; RUN: -check-prefix=MIPS24; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \5; RUN: -check-prefix=MIPS326; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \7; RUN: -check-prefix=MIPS32R28; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \9; RUN: -check-prefix=MIPS32R210; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \11; RUN: -check-prefix=MIPS32R212; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \13; RUN: -check-prefix=MIPS32R614; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \15; RUN: -check-prefix=MIPS316; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \17; RUN: -check-prefix=MIPS418; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \19; RUN: -check-prefix=MIPS6420; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \21; RUN: -check-prefix=MIPS64R222; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \23; RUN: -check-prefix=MIPS64R224; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \25; RUN: -check-prefix=MIPS64R226; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \27; RUN: -check-prefix=MIPS64R628; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \29; RUN: -check-prefix=MMR330; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \31; RUN: -check-prefix=MMR632 33define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {34; MIPS2-LABEL: lshr_i1:35; MIPS2: # %bb.0: # %entry36; MIPS2-NEXT: jr $ra37; MIPS2-NEXT: move $2, $438;39; MIPS32-LABEL: lshr_i1:40; MIPS32: # %bb.0: # %entry41; MIPS32-NEXT: jr $ra42; MIPS32-NEXT: move $2, $443;44; MIPS32R2-LABEL: lshr_i1:45; MIPS32R2: # %bb.0: # %entry46; MIPS32R2-NEXT: jr $ra47; MIPS32R2-NEXT: move $2, $448;49; MIPS32R6-LABEL: lshr_i1:50; MIPS32R6: # %bb.0: # %entry51; MIPS32R6-NEXT: jr $ra52; MIPS32R6-NEXT: move $2, $453;54; MIPS3-LABEL: lshr_i1:55; MIPS3: # %bb.0: # %entry56; MIPS3-NEXT: jr $ra57; MIPS3-NEXT: move $2, $458;59; MIPS4-LABEL: lshr_i1:60; MIPS4: # %bb.0: # %entry61; MIPS4-NEXT: jr $ra62; MIPS4-NEXT: move $2, $463;64; MIPS64-LABEL: lshr_i1:65; MIPS64: # %bb.0: # %entry66; MIPS64-NEXT: jr $ra67; MIPS64-NEXT: move $2, $468;69; MIPS64R2-LABEL: lshr_i1:70; MIPS64R2: # %bb.0: # %entry71; MIPS64R2-NEXT: jr $ra72; MIPS64R2-NEXT: move $2, $473;74; MIPS64R6-LABEL: lshr_i1:75; MIPS64R6: # %bb.0: # %entry76; MIPS64R6-NEXT: jr $ra77; MIPS64R6-NEXT: move $2, $478;79; MMR3-LABEL: lshr_i1:80; MMR3: # %bb.0: # %entry81; MMR3-NEXT: move $2, $482; MMR3-NEXT: jrc $ra83;84; MMR6-LABEL: lshr_i1:85; MMR6: # %bb.0: # %entry86; MMR6-NEXT: move $2, $487; MMR6-NEXT: jrc $ra88entry:89 90 %r = lshr i1 %a, %b91 ret i1 %r92}93 94define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {95; MIPS2-LABEL: lshr_i8:96; MIPS2: # %bb.0: # %entry97; MIPS2-NEXT: jr $ra98; MIPS2-NEXT: srlv $2, $4, $599;100; MIPS32-LABEL: lshr_i8:101; MIPS32: # %bb.0: # %entry102; MIPS32-NEXT: jr $ra103; MIPS32-NEXT: srlv $2, $4, $5104;105; MIPS32R2-LABEL: lshr_i8:106; MIPS32R2: # %bb.0: # %entry107; MIPS32R2-NEXT: jr $ra108; MIPS32R2-NEXT: srlv $2, $4, $5109;110; MIPS32R6-LABEL: lshr_i8:111; MIPS32R6: # %bb.0: # %entry112; MIPS32R6-NEXT: jr $ra113; MIPS32R6-NEXT: srlv $2, $4, $5114;115; MIPS3-LABEL: lshr_i8:116; MIPS3: # %bb.0: # %entry117; MIPS3-NEXT: jr $ra118; MIPS3-NEXT: srlv $2, $4, $5119;120; MIPS4-LABEL: lshr_i8:121; MIPS4: # %bb.0: # %entry122; MIPS4-NEXT: jr $ra123; MIPS4-NEXT: srlv $2, $4, $5124;125; MIPS64-LABEL: lshr_i8:126; MIPS64: # %bb.0: # %entry127; MIPS64-NEXT: jr $ra128; MIPS64-NEXT: srlv $2, $4, $5129;130; MIPS64R2-LABEL: lshr_i8:131; MIPS64R2: # %bb.0: # %entry132; MIPS64R2-NEXT: jr $ra133; MIPS64R2-NEXT: srlv $2, $4, $5134;135; MIPS64R6-LABEL: lshr_i8:136; MIPS64R6: # %bb.0: # %entry137; MIPS64R6-NEXT: jr $ra138; MIPS64R6-NEXT: srlv $2, $4, $5139;140; MMR3-LABEL: lshr_i8:141; MMR3: # %bb.0: # %entry142; MMR3-NEXT: jr $ra143; MMR3-NEXT: srlv $2, $4, $5144;145; MMR6-LABEL: lshr_i8:146; MMR6: # %bb.0: # %entry147; MMR6-NEXT: srlv $2, $4, $5148; MMR6-NEXT: jrc $ra149entry:150 151 %r = lshr i8 %a, %b152 ret i8 %r153}154 155define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {156; MIPS2-LABEL: lshr_i16:157; MIPS2: # %bb.0: # %entry158; MIPS2-NEXT: jr $ra159; MIPS2-NEXT: srlv $2, $4, $5160;161; MIPS32-LABEL: lshr_i16:162; MIPS32: # %bb.0: # %entry163; MIPS32-NEXT: jr $ra164; MIPS32-NEXT: srlv $2, $4, $5165;166; MIPS32R2-LABEL: lshr_i16:167; MIPS32R2: # %bb.0: # %entry168; MIPS32R2-NEXT: jr $ra169; MIPS32R2-NEXT: srlv $2, $4, $5170;171; MIPS32R6-LABEL: lshr_i16:172; MIPS32R6: # %bb.0: # %entry173; MIPS32R6-NEXT: jr $ra174; MIPS32R6-NEXT: srlv $2, $4, $5175;176; MIPS3-LABEL: lshr_i16:177; MIPS3: # %bb.0: # %entry178; MIPS3-NEXT: jr $ra179; MIPS3-NEXT: srlv $2, $4, $5180;181; MIPS4-LABEL: lshr_i16:182; MIPS4: # %bb.0: # %entry183; MIPS4-NEXT: jr $ra184; MIPS4-NEXT: srlv $2, $4, $5185;186; MIPS64-LABEL: lshr_i16:187; MIPS64: # %bb.0: # %entry188; MIPS64-NEXT: jr $ra189; MIPS64-NEXT: srlv $2, $4, $5190;191; MIPS64R2-LABEL: lshr_i16:192; MIPS64R2: # %bb.0: # %entry193; MIPS64R2-NEXT: jr $ra194; MIPS64R2-NEXT: srlv $2, $4, $5195;196; MIPS64R6-LABEL: lshr_i16:197; MIPS64R6: # %bb.0: # %entry198; MIPS64R6-NEXT: jr $ra199; MIPS64R6-NEXT: srlv $2, $4, $5200;201; MMR3-LABEL: lshr_i16:202; MMR3: # %bb.0: # %entry203; MMR3-NEXT: jr $ra204; MMR3-NEXT: srlv $2, $4, $5205;206; MMR6-LABEL: lshr_i16:207; MMR6: # %bb.0: # %entry208; MMR6-NEXT: srlv $2, $4, $5209; MMR6-NEXT: jrc $ra210entry:211 212 %r = lshr i16 %a, %b213 ret i16 %r214}215 216define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {217; MIPS2-LABEL: lshr_i32:218; MIPS2: # %bb.0: # %entry219; MIPS2-NEXT: jr $ra220; MIPS2-NEXT: srlv $2, $4, $5221;222; MIPS32-LABEL: lshr_i32:223; MIPS32: # %bb.0: # %entry224; MIPS32-NEXT: jr $ra225; MIPS32-NEXT: srlv $2, $4, $5226;227; MIPS32R2-LABEL: lshr_i32:228; MIPS32R2: # %bb.0: # %entry229; MIPS32R2-NEXT: jr $ra230; MIPS32R2-NEXT: srlv $2, $4, $5231;232; MIPS32R6-LABEL: lshr_i32:233; MIPS32R6: # %bb.0: # %entry234; MIPS32R6-NEXT: jr $ra235; MIPS32R6-NEXT: srlv $2, $4, $5236;237; MIPS3-LABEL: lshr_i32:238; MIPS3: # %bb.0: # %entry239; MIPS3-NEXT: jr $ra240; MIPS3-NEXT: srlv $2, $4, $5241;242; MIPS4-LABEL: lshr_i32:243; MIPS4: # %bb.0: # %entry244; MIPS4-NEXT: jr $ra245; MIPS4-NEXT: srlv $2, $4, $5246;247; MIPS64-LABEL: lshr_i32:248; MIPS64: # %bb.0: # %entry249; MIPS64-NEXT: jr $ra250; MIPS64-NEXT: srlv $2, $4, $5251;252; MIPS64R2-LABEL: lshr_i32:253; MIPS64R2: # %bb.0: # %entry254; MIPS64R2-NEXT: jr $ra255; MIPS64R2-NEXT: srlv $2, $4, $5256;257; MIPS64R6-LABEL: lshr_i32:258; MIPS64R6: # %bb.0: # %entry259; MIPS64R6-NEXT: jr $ra260; MIPS64R6-NEXT: srlv $2, $4, $5261;262; MMR3-LABEL: lshr_i32:263; MMR3: # %bb.0: # %entry264; MMR3-NEXT: jr $ra265; MMR3-NEXT: srlv $2, $4, $5266;267; MMR6-LABEL: lshr_i32:268; MMR6: # %bb.0: # %entry269; MMR6-NEXT: srlv $2, $4, $5270; MMR6-NEXT: jrc $ra271entry:272 273 %r = lshr i32 %a, %b274 ret i32 %r275}276 277define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {278; MIPS2-LABEL: lshr_i64:279; MIPS2: # %bb.0: # %entry280; MIPS2-NEXT: srlv $6, $4, $7281; MIPS2-NEXT: andi $1, $7, 32282; MIPS2-NEXT: bnez $1, $BB4_2283; MIPS2-NEXT: addiu $2, $zero, 0284; MIPS2-NEXT: # %bb.1: # %entry285; MIPS2-NEXT: srlv $1, $5, $7286; MIPS2-NEXT: xori $2, $7, 31287; MIPS2-NEXT: sll $3, $4, 1288; MIPS2-NEXT: sllv $2, $3, $2289; MIPS2-NEXT: or $3, $2, $1290; MIPS2-NEXT: jr $ra291; MIPS2-NEXT: move $2, $6292; MIPS2-NEXT: $BB4_2:293; MIPS2-NEXT: jr $ra294; MIPS2-NEXT: move $3, $6295;296; MIPS32-LABEL: lshr_i64:297; MIPS32: # %bb.0: # %entry298; MIPS32-NEXT: srlv $1, $5, $7299; MIPS32-NEXT: xori $2, $7, 31300; MIPS32-NEXT: sll $3, $4, 1301; MIPS32-NEXT: sllv $2, $3, $2302; MIPS32-NEXT: or $3, $2, $1303; MIPS32-NEXT: srlv $2, $4, $7304; MIPS32-NEXT: andi $1, $7, 32305; MIPS32-NEXT: movn $3, $2, $1306; MIPS32-NEXT: jr $ra307; MIPS32-NEXT: movn $2, $zero, $1308;309; MIPS32R2-LABEL: lshr_i64:310; MIPS32R2: # %bb.0: # %entry311; MIPS32R2-NEXT: srlv $1, $5, $7312; MIPS32R2-NEXT: xori $2, $7, 31313; MIPS32R2-NEXT: sll $3, $4, 1314; MIPS32R2-NEXT: sllv $2, $3, $2315; MIPS32R2-NEXT: or $3, $2, $1316; MIPS32R2-NEXT: srlv $2, $4, $7317; MIPS32R2-NEXT: andi $1, $7, 32318; MIPS32R2-NEXT: movn $3, $2, $1319; MIPS32R2-NEXT: jr $ra320; MIPS32R2-NEXT: movn $2, $zero, $1321;322; MIPS32R6-LABEL: lshr_i64:323; MIPS32R6: # %bb.0: # %entry324; MIPS32R6-NEXT: srlv $1, $5, $7325; MIPS32R6-NEXT: xori $2, $7, 31326; MIPS32R6-NEXT: sll $3, $4, 1327; MIPS32R6-NEXT: sllv $2, $3, $2328; MIPS32R6-NEXT: or $1, $2, $1329; MIPS32R6-NEXT: andi $2, $7, 32330; MIPS32R6-NEXT: seleqz $1, $1, $2331; MIPS32R6-NEXT: srlv $4, $4, $7332; MIPS32R6-NEXT: selnez $3, $4, $2333; MIPS32R6-NEXT: or $3, $3, $1334; MIPS32R6-NEXT: jr $ra335; MIPS32R6-NEXT: seleqz $2, $4, $2336;337; MIPS3-LABEL: lshr_i64:338; MIPS3: # %bb.0: # %entry339; MIPS3-NEXT: jr $ra340; MIPS3-NEXT: dsrlv $2, $4, $5341;342; MIPS4-LABEL: lshr_i64:343; MIPS4: # %bb.0: # %entry344; MIPS4-NEXT: jr $ra345; MIPS4-NEXT: dsrlv $2, $4, $5346;347; MIPS64-LABEL: lshr_i64:348; MIPS64: # %bb.0: # %entry349; MIPS64-NEXT: jr $ra350; MIPS64-NEXT: dsrlv $2, $4, $5351;352; MIPS64R2-LABEL: lshr_i64:353; MIPS64R2: # %bb.0: # %entry354; MIPS64R2-NEXT: jr $ra355; MIPS64R2-NEXT: dsrlv $2, $4, $5356;357; MIPS64R6-LABEL: lshr_i64:358; MIPS64R6: # %bb.0: # %entry359; MIPS64R6-NEXT: jr $ra360; MIPS64R6-NEXT: dsrlv $2, $4, $5361;362; MMR3-LABEL: lshr_i64:363; MMR3: # %bb.0: # %entry364; MMR3-NEXT: srlv $2, $5, $7365; MMR3-NEXT: xori $1, $7, 31366; MMR3-NEXT: sll16 $3, $4, 1367; MMR3-NEXT: sllv $3, $3, $1368; MMR3-NEXT: or16 $3, $2369; MMR3-NEXT: srlv $2, $4, $7370; MMR3-NEXT: andi16 $4, $7, 32371; MMR3-NEXT: movn $3, $2, $4372; MMR3-NEXT: li16 $5, 0373; MMR3-NEXT: jr $ra374; MMR3-NEXT: movn $2, $5, $4375;376; MMR6-LABEL: lshr_i64:377; MMR6: # %bb.0: # %entry378; MMR6-NEXT: srlv $1, $5, $7379; MMR6-NEXT: xori $2, $7, 31380; MMR6-NEXT: sll16 $3, $4, 1381; MMR6-NEXT: sllv $2, $3, $2382; MMR6-NEXT: or $1, $2, $1383; MMR6-NEXT: andi16 $2, $7, 32384; MMR6-NEXT: seleqz $1, $1, $2385; MMR6-NEXT: srlv $4, $4, $7386; MMR6-NEXT: selnez $3, $4, $2387; MMR6-NEXT: or $3, $3, $1388; MMR6-NEXT: seleqz $2, $4, $2389; MMR6-NEXT: jrc $ra390entry:391 392 %r = lshr i64 %a, %b393 ret i64 %r394}395 396define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {397; MIPS2-LABEL: lshr_i128:398; MIPS2: # %bb.0: # %entry399; MIPS2-NEXT: addiu $sp, $sp, -32400; MIPS2-NEXT: .cfi_def_cfa_offset 32401; MIPS2-NEXT: addiu $1, $sp, 0402; MIPS2-NEXT: sw $7, 28($sp)403; MIPS2-NEXT: sw $6, 24($sp)404; MIPS2-NEXT: sw $5, 20($sp)405; MIPS2-NEXT: sw $4, 16($sp)406; MIPS2-NEXT: addiu $1, $1, 16407; MIPS2-NEXT: lw $2, 60($sp)408; MIPS2-NEXT: srl $3, $2, 3409; MIPS2-NEXT: andi $3, $3, 12410; MIPS2-NEXT: subu $1, $1, $3411; MIPS2-NEXT: sw $zero, 12($sp)412; MIPS2-NEXT: sw $zero, 8($sp)413; MIPS2-NEXT: sw $zero, 4($sp)414; MIPS2-NEXT: sw $zero, 0($sp)415; MIPS2-NEXT: lw $3, 4($1)416; MIPS2-NEXT: lw $5, 8($1)417; MIPS2-NEXT: srlv $4, $5, $2418; MIPS2-NEXT: sll $6, $3, 1419; MIPS2-NEXT: andi $7, $2, 31420; MIPS2-NEXT: xori $7, $7, 31421; MIPS2-NEXT: sllv $6, $6, $7422; MIPS2-NEXT: srlv $3, $3, $2423; MIPS2-NEXT: lw $8, 0($1)424; MIPS2-NEXT: sll $9, $8, 1425; MIPS2-NEXT: sllv $9, $9, $7426; MIPS2-NEXT: or $3, $3, $9427; MIPS2-NEXT: or $4, $4, $6428; MIPS2-NEXT: lw $1, 12($1)429; MIPS2-NEXT: srlv $1, $1, $2430; MIPS2-NEXT: sll $5, $5, 1431; MIPS2-NEXT: sllv $5, $5, $7432; MIPS2-NEXT: or $5, $1, $5433; MIPS2-NEXT: srlv $2, $8, $2434; MIPS2-NEXT: jr $ra435; MIPS2-NEXT: addiu $sp, $sp, 32436;437; MIPS32-LABEL: lshr_i128:438; MIPS32: # %bb.0: # %entry439; MIPS32-NEXT: addiu $sp, $sp, -32440; MIPS32-NEXT: .cfi_def_cfa_offset 32441; MIPS32-NEXT: addiu $1, $sp, 0442; MIPS32-NEXT: sw $7, 28($sp)443; MIPS32-NEXT: sw $6, 24($sp)444; MIPS32-NEXT: sw $5, 20($sp)445; MIPS32-NEXT: sw $4, 16($sp)446; MIPS32-NEXT: addiu $1, $1, 16447; MIPS32-NEXT: lw $2, 60($sp)448; MIPS32-NEXT: srl $3, $2, 3449; MIPS32-NEXT: andi $3, $3, 12450; MIPS32-NEXT: subu $1, $1, $3451; MIPS32-NEXT: sw $zero, 12($sp)452; MIPS32-NEXT: sw $zero, 8($sp)453; MIPS32-NEXT: sw $zero, 4($sp)454; MIPS32-NEXT: sw $zero, 0($sp)455; MIPS32-NEXT: lw $3, 4($1)456; MIPS32-NEXT: lw $5, 8($1)457; MIPS32-NEXT: srlv $4, $5, $2458; MIPS32-NEXT: sll $6, $3, 1459; MIPS32-NEXT: andi $7, $2, 31460; MIPS32-NEXT: xori $7, $7, 31461; MIPS32-NEXT: sllv $6, $6, $7462; MIPS32-NEXT: srlv $3, $3, $2463; MIPS32-NEXT: lw $8, 0($1)464; MIPS32-NEXT: sll $9, $8, 1465; MIPS32-NEXT: sllv $9, $9, $7466; MIPS32-NEXT: or $3, $3, $9467; MIPS32-NEXT: or $4, $4, $6468; MIPS32-NEXT: lw $1, 12($1)469; MIPS32-NEXT: srlv $1, $1, $2470; MIPS32-NEXT: sll $5, $5, 1471; MIPS32-NEXT: sllv $5, $5, $7472; MIPS32-NEXT: or $5, $1, $5473; MIPS32-NEXT: srlv $2, $8, $2474; MIPS32-NEXT: jr $ra475; MIPS32-NEXT: addiu $sp, $sp, 32476;477; MIPS32R2-LABEL: lshr_i128:478; MIPS32R2: # %bb.0: # %entry479; MIPS32R2-NEXT: addiu $sp, $sp, -32480; MIPS32R2-NEXT: .cfi_def_cfa_offset 32481; MIPS32R2-NEXT: addiu $1, $sp, 0482; MIPS32R2-NEXT: sw $7, 28($sp)483; MIPS32R2-NEXT: sw $6, 24($sp)484; MIPS32R2-NEXT: sw $5, 20($sp)485; MIPS32R2-NEXT: sw $4, 16($sp)486; MIPS32R2-NEXT: addiu $1, $1, 16487; MIPS32R2-NEXT: lw $2, 60($sp)488; MIPS32R2-NEXT: srl $3, $2, 3489; MIPS32R2-NEXT: andi $3, $3, 12490; MIPS32R2-NEXT: subu $1, $1, $3491; MIPS32R2-NEXT: sw $zero, 12($sp)492; MIPS32R2-NEXT: sw $zero, 8($sp)493; MIPS32R2-NEXT: sw $zero, 4($sp)494; MIPS32R2-NEXT: sw $zero, 0($sp)495; MIPS32R2-NEXT: lw $3, 4($1)496; MIPS32R2-NEXT: lw $5, 8($1)497; MIPS32R2-NEXT: srlv $4, $5, $2498; MIPS32R2-NEXT: sll $6, $3, 1499; MIPS32R2-NEXT: andi $7, $2, 31500; MIPS32R2-NEXT: xori $7, $7, 31501; MIPS32R2-NEXT: sllv $6, $6, $7502; MIPS32R2-NEXT: srlv $3, $3, $2503; MIPS32R2-NEXT: lw $8, 0($1)504; MIPS32R2-NEXT: sll $9, $8, 1505; MIPS32R2-NEXT: sllv $9, $9, $7506; MIPS32R2-NEXT: or $3, $3, $9507; MIPS32R2-NEXT: or $4, $4, $6508; MIPS32R2-NEXT: lw $1, 12($1)509; MIPS32R2-NEXT: srlv $1, $1, $2510; MIPS32R2-NEXT: sll $5, $5, 1511; MIPS32R2-NEXT: sllv $5, $5, $7512; MIPS32R2-NEXT: or $5, $1, $5513; MIPS32R2-NEXT: srlv $2, $8, $2514; MIPS32R2-NEXT: jr $ra515; MIPS32R2-NEXT: addiu $sp, $sp, 32516;517; MIPS32R6-LABEL: lshr_i128:518; MIPS32R6: # %bb.0: # %entry519; MIPS32R6-NEXT: addiu $sp, $sp, -32520; MIPS32R6-NEXT: .cfi_def_cfa_offset 32521; MIPS32R6-NEXT: addiu $1, $sp, 0522; MIPS32R6-NEXT: sw $7, 28($sp)523; MIPS32R6-NEXT: sw $6, 24($sp)524; MIPS32R6-NEXT: sw $5, 20($sp)525; MIPS32R6-NEXT: sw $4, 16($sp)526; MIPS32R6-NEXT: addiu $1, $1, 16527; MIPS32R6-NEXT: lw $2, 60($sp)528; MIPS32R6-NEXT: srl $3, $2, 3529; MIPS32R6-NEXT: andi $3, $3, 12530; MIPS32R6-NEXT: subu $1, $1, $3531; MIPS32R6-NEXT: sw $zero, 12($sp)532; MIPS32R6-NEXT: sw $zero, 8($sp)533; MIPS32R6-NEXT: sw $zero, 4($sp)534; MIPS32R6-NEXT: sw $zero, 0($sp)535; MIPS32R6-NEXT: lw $3, 4($1)536; MIPS32R6-NEXT: lw $5, 8($1)537; MIPS32R6-NEXT: srlv $4, $5, $2538; MIPS32R6-NEXT: sll $6, $3, 1539; MIPS32R6-NEXT: andi $7, $2, 31540; MIPS32R6-NEXT: xori $7, $7, 31541; MIPS32R6-NEXT: sllv $6, $6, $7542; MIPS32R6-NEXT: srlv $3, $3, $2543; MIPS32R6-NEXT: lw $8, 0($1)544; MIPS32R6-NEXT: sll $9, $8, 1545; MIPS32R6-NEXT: sllv $9, $9, $7546; MIPS32R6-NEXT: or $3, $3, $9547; MIPS32R6-NEXT: or $4, $4, $6548; MIPS32R6-NEXT: lw $1, 12($1)549; MIPS32R6-NEXT: srlv $1, $1, $2550; MIPS32R6-NEXT: sll $5, $5, 1551; MIPS32R6-NEXT: sllv $5, $5, $7552; MIPS32R6-NEXT: or $5, $1, $5553; MIPS32R6-NEXT: srlv $2, $8, $2554; MIPS32R6-NEXT: jr $ra555; MIPS32R6-NEXT: addiu $sp, $sp, 32556;557; MIPS3-LABEL: lshr_i128:558; MIPS3: # %bb.0: # %entry559; MIPS3-NEXT: sll $3, $7, 0560; MIPS3-NEXT: dsrlv $6, $4, $7561; MIPS3-NEXT: andi $1, $3, 64562; MIPS3-NEXT: bnez $1, .LBB5_2563; MIPS3-NEXT: daddiu $2, $zero, 0564; MIPS3-NEXT: # %bb.1: # %entry565; MIPS3-NEXT: dsrlv $1, $5, $7566; MIPS3-NEXT: dsll $2, $4, 1567; MIPS3-NEXT: xori $3, $3, 63568; MIPS3-NEXT: dsllv $2, $2, $3569; MIPS3-NEXT: or $3, $2, $1570; MIPS3-NEXT: jr $ra571; MIPS3-NEXT: move $2, $6572; MIPS3-NEXT: .LBB5_2:573; MIPS3-NEXT: jr $ra574; MIPS3-NEXT: move $3, $6575;576; MIPS4-LABEL: lshr_i128:577; MIPS4: # %bb.0: # %entry578; MIPS4-NEXT: dsrlv $1, $5, $7579; MIPS4-NEXT: dsll $2, $4, 1580; MIPS4-NEXT: sll $5, $7, 0581; MIPS4-NEXT: xori $3, $5, 63582; MIPS4-NEXT: dsllv $2, $2, $3583; MIPS4-NEXT: or $3, $2, $1584; MIPS4-NEXT: dsrlv $2, $4, $7585; MIPS4-NEXT: andi $1, $5, 64586; MIPS4-NEXT: movn $3, $2, $1587; MIPS4-NEXT: jr $ra588; MIPS4-NEXT: movn $2, $zero, $1589;590; MIPS64-LABEL: lshr_i128:591; MIPS64: # %bb.0: # %entry592; MIPS64-NEXT: dsrlv $1, $5, $7593; MIPS64-NEXT: dsll $2, $4, 1594; MIPS64-NEXT: sll $5, $7, 0595; MIPS64-NEXT: xori $3, $5, 63596; MIPS64-NEXT: dsllv $2, $2, $3597; MIPS64-NEXT: or $3, $2, $1598; MIPS64-NEXT: dsrlv $2, $4, $7599; MIPS64-NEXT: andi $1, $5, 64600; MIPS64-NEXT: movn $3, $2, $1601; MIPS64-NEXT: jr $ra602; MIPS64-NEXT: movn $2, $zero, $1603;604; MIPS64R2-LABEL: lshr_i128:605; MIPS64R2: # %bb.0: # %entry606; MIPS64R2-NEXT: dsrlv $1, $5, $7607; MIPS64R2-NEXT: dsll $2, $4, 1608; MIPS64R2-NEXT: sll $5, $7, 0609; MIPS64R2-NEXT: xori $3, $5, 63610; MIPS64R2-NEXT: dsllv $2, $2, $3611; MIPS64R2-NEXT: or $3, $2, $1612; MIPS64R2-NEXT: dsrlv $2, $4, $7613; MIPS64R2-NEXT: andi $1, $5, 64614; MIPS64R2-NEXT: movn $3, $2, $1615; MIPS64R2-NEXT: jr $ra616; MIPS64R2-NEXT: movn $2, $zero, $1617;618; MIPS64R6-LABEL: lshr_i128:619; MIPS64R6: # %bb.0: # %entry620; MIPS64R6-NEXT: dsrlv $1, $5, $7621; MIPS64R6-NEXT: dsll $2, $4, 1622; MIPS64R6-NEXT: sll $3, $7, 0623; MIPS64R6-NEXT: xori $5, $3, 63624; MIPS64R6-NEXT: dsllv $2, $2, $5625; MIPS64R6-NEXT: or $1, $2, $1626; MIPS64R6-NEXT: andi $2, $3, 64627; MIPS64R6-NEXT: sll $2, $2, 0628; MIPS64R6-NEXT: seleqz $1, $1, $2629; MIPS64R6-NEXT: dsrlv $4, $4, $7630; MIPS64R6-NEXT: selnez $3, $4, $2631; MIPS64R6-NEXT: or $3, $3, $1632; MIPS64R6-NEXT: jr $ra633; MIPS64R6-NEXT: seleqz $2, $4, $2634;635; MMR3-LABEL: lshr_i128:636; MMR3: # %bb.0: # %entry637; MMR3-NEXT: addiusp -40638; MMR3-NEXT: .cfi_def_cfa_offset 40639; MMR3-NEXT: swp $16, 32($sp)640; MMR3-NEXT: .cfi_offset 17, -4641; MMR3-NEXT: .cfi_offset 16, -8642; MMR3-NEXT: li16 $2, 0643; MMR3-NEXT: swp $6, 24($sp)644; MMR3-NEXT: swp $4, 16($sp)645; MMR3-NEXT: sw $2, 12($sp)646; MMR3-NEXT: sw $2, 8($sp)647; MMR3-NEXT: sw $2, 4($sp)648; MMR3-NEXT: sw $2, 0($sp)649; MMR3-NEXT: addiur1sp $2, 0650; MMR3-NEXT: addiur2 $2, $2, 16651; MMR3-NEXT: lw $3, 68($sp)652; MMR3-NEXT: srl16 $4, $3, 3653; MMR3-NEXT: andi $4, $4, 12654; MMR3-NEXT: subu16 $5, $2, $4655; MMR3-NEXT: lwp $6, 4($5)656; MMR3-NEXT: andi16 $2, $3, 31657; MMR3-NEXT: srlv $16, $7, $2658; MMR3-NEXT: sll16 $3, $6, 1659; MMR3-NEXT: xori $1, $2, 31660; MMR3-NEXT: sllv $4, $3, $1661; MMR3-NEXT: srlv $6, $6, $2662; MMR3-NEXT: lw16 $17, 0($5)663; MMR3-NEXT: sll16 $3, $17, 1664; MMR3-NEXT: sllv $3, $3, $1665; MMR3-NEXT: or16 $3, $6666; MMR3-NEXT: or16 $4, $16667; MMR3-NEXT: lw16 $5, 12($5)668; MMR3-NEXT: srlv $6, $5, $2669; MMR3-NEXT: sll16 $5, $7, 1670; MMR3-NEXT: sllv $5, $5, $1671; MMR3-NEXT: or16 $5, $6672; MMR3-NEXT: srlv $2, $17, $2673; MMR3-NEXT: lwp $16, 32($sp)674; MMR3-NEXT: addiusp 40675; MMR3-NEXT: jrc $ra676;677; MMR6-LABEL: lshr_i128:678; MMR6: # %bb.0: # %entry679; MMR6-NEXT: addiu $sp, $sp, -40680; MMR6-NEXT: .cfi_def_cfa_offset 40681; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill682; MMR6-NEXT: .cfi_offset 16, -4683; MMR6-NEXT: li16 $2, 0684; MMR6-NEXT: sw $7, 28($sp)685; MMR6-NEXT: sw $6, 24($sp)686; MMR6-NEXT: sw $5, 20($sp)687; MMR6-NEXT: sw $4, 16($sp)688; MMR6-NEXT: sw $2, 12($sp)689; MMR6-NEXT: sw $2, 8($sp)690; MMR6-NEXT: sw $2, 4($sp)691; MMR6-NEXT: sw $2, 0($sp)692; MMR6-NEXT: addiu $2, $sp, 0693; MMR6-NEXT: addiur2 $2, $2, 16694; MMR6-NEXT: lw $3, 68($sp)695; MMR6-NEXT: srl16 $4, $3, 3696; MMR6-NEXT: andi $4, $4, 12697; MMR6-NEXT: subu16 $2, $2, $4698; MMR6-NEXT: lw16 $4, 4($2)699; MMR6-NEXT: lw16 $5, 8($2)700; MMR6-NEXT: andi16 $6, $3, 31701; MMR6-NEXT: srlv $1, $5, $6702; MMR6-NEXT: sll16 $3, $4, 1703; MMR6-NEXT: xori $7, $6, 31704; MMR6-NEXT: sllv $8, $3, $7705; MMR6-NEXT: srlv $3, $4, $6706; MMR6-NEXT: lw16 $16, 0($2)707; MMR6-NEXT: sll16 $4, $16, 1708; MMR6-NEXT: sllv $4, $4, $7709; MMR6-NEXT: or $3, $3, $4710; MMR6-NEXT: or $4, $1, $8711; MMR6-NEXT: lw16 $2, 12($2)712; MMR6-NEXT: srlv $1, $2, $6713; MMR6-NEXT: sll16 $2, $5, 1714; MMR6-NEXT: sllv $2, $2, $7715; MMR6-NEXT: or $5, $1, $2716; MMR6-NEXT: srlv $2, $16, $6717; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload718; MMR6-NEXT: addiu $sp, $sp, 40719; MMR6-NEXT: jrc $ra720entry:721 722; o32 shouldn't use TImode helpers.723; GP32-NOT: lw $25, %call16(__lshrti3)($gp)724; MM-NOT: lw $25, %call16(__lshrti3)($2)725 726 %r = lshr i128 %a, %b727 ret i128 %r728}729