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1; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic | \2; RUN: FileCheck %s -check-prefixes=ALL,M2,GP323; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic | \4; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP325; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic | \6; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP327; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic | \8; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP329; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic | \10; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP3211; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic | \12; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP3213; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic | \14; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R615; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic | \16; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R617; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic | \18; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R619; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic | \20; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R621; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic | \22; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R623; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic | \24; RUN: FileCheck %s -check-prefixes=ALL,64R625; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \26; RUN: FileCheck %s -check-prefixes=MM32,MM32R327; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \28; RUN: FileCheck %s -check-prefixes=MM32,MM32R629 30define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {31entry:32; ALL-LABEL: mul_i1:33 34 ; M2: and $[[T0:[0-9]+]], $4, $535 36 ; 32R1-R5: and $[[T0:[0-9]+]], $4, $537 38 ; 32R6: and $[[T0:[0-9]+]], $4, $539 40 ; M4: and $[[T0:[0-9]+]], $4, $541 42 ; 64R1-R5: and $[[T0:[0-9]+]], $4, $543 44 ; 64R6: and $[[T0:[0-9]+]], $4, $545 46 ; MM32R3: and16 $4, $547 ; MM32R3: move $2, $448 49 ; MM32R6: and $[[T0:[0-9]+]], $4, $550 51 %r = mul i1 %a, %b52 ret i1 %r53}54 55define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {56entry:57; ALL-LABEL: mul_i8:58 59 ; M2: mult $4, $560 ; M2: mflo $[[T0:[0-9]+]]61 ; M2: sll $[[T0]], $[[T0]], 2462 ; M2: sra $2, $[[T0]], 2463 64 ; 32R1: mul $[[T0:[0-9]+]], $4, $565 ; 32R1: sll $[[T0]], $[[T0]], 2466 ; 32R1: sra $2, $[[T0]], 2467 68 ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $569 ; 32R2-R5: seb $2, $[[T0]]70 71 ; 32R6: mul $[[T0:[0-9]+]], $4, $572 ; 32R6: seb $2, $[[T0]]73 74 ; M4: mult $4, $575 ; M4: mflo $[[T0:[0-9]+]]76 ; M4: sll $[[T0]], $[[T0]], 2477 ; M4: sra $2, $[[T0]], 2478 79 ; 64R1: mul $[[T0:[0-9]+]], $4, $580 ; 64R1: sll $[[T0]], $[[T0]], 2481 ; 64R1: sra $2, $[[T0]], 2482 83 ; 64R2: mul $[[T0:[0-9]+]], $4, $584 ; 64R2: seb $2, $[[T0]]85 86 ; 64R6: mul $[[T0:[0-9]+]], $4, $587 ; 64R6: seb $2, $[[T0]]88 89 ; MM32: mul $[[T0:[0-9]+]], $4, $590 ; MM32: seb $2, $[[T0]]91 92 %r = mul i8 %a, %b93 ret i8 %r94}95 96define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {97entry:98; ALL-LABEL: mul_i16:99 100 ; M2: mult $4, $5101 ; M2: mflo $[[T0:[0-9]+]]102 ; M2: sll $[[T0]], $[[T0]], 16103 ; M2: sra $2, $[[T0]], 16104 105 ; 32R1: mul $[[T0:[0-9]+]], $4, $5106 ; 32R1: sll $[[T0]], $[[T0]], 16107 ; 32R1: sra $2, $[[T0]], 16108 109 ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5110 ; 32R2-R5: seh $2, $[[T0]]111 112 ; 32R6: mul $[[T0:[0-9]+]], $4, $5113 ; 32R6: seh $2, $[[T0]]114 115 ; M4: mult $4, $5116 ; M4: mflo $[[T0:[0-9]+]]117 ; M4: sll $[[T0]], $[[T0]], 16118 ; M4: sra $2, $[[T0]], 16119 120 ; 64R1: mul $[[T0:[0-9]+]], $4, $5121 ; 64R1: sll $[[T0]], $[[T0]], 16122 ; 64R1: sra $2, $[[T0]], 16123 124 ; 64R2: mul $[[T0:[0-9]+]], $4, $5125 ; 64R2: seh $2, $[[T0]]126 127 ; 64R6: mul $[[T0:[0-9]+]], $4, $5128 ; 64R6: seh $2, $[[T0]]129 130 ; MM32: mul $[[T0:[0-9]+]], $4, $5131 ; MM32: seh $2, $[[T0]]132 133 %r = mul i16 %a, %b134 ret i16 %r135}136 137define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {138entry:139; ALL-LABEL: mul_i32:140 141 ; M2: mult $4, $5142 ; M2: mflo $2143 144 ; M4: mult $4, $5145 ; M4: mflo $1146 147 ; 32R1-R5: mul $2, $4, $5148 ; 32R6: mul $2, $4, $5149 150 ; 64R1-R5: mul $2, $4, $5151 ; 64R6: mul $2, $4, $5152 153 ; MM32: mul $2, $4, $5154 155 %r = mul i32 %a, %b156 ret i32 %r157}158 159define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {160entry:161; ALL-LABEL: mul_i64:162 163 ; M2: mult $4, $7164 ; M2: mflo $[[T0:[0-9]+]]165 ; M2: mult $5, $6166 ; M2: mflo $[[T1:[0-9]+]]167 ; M2: multu $5, $7168 ; M2: mflo $3169 ; M2: mfhi $4170 ; M2: addu $[[T2:[0-9]+]], $4, $[[T1]]171 ; M2: addu $2, $[[T2]], $[[T0]]172 173 ; 32R1-R5: multu $5, $7174 ; 32R1-R5: mflo $3175 ; 32R1-R5: mfhi $[[T0:[0-9]+]]176 ; 32R1-R5: mul $[[T1:[0-9]+]], $5, $6177 ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T1:[0-9]+]]178 ; 32R1-R5: mul $[[T2:[0-9]+]], $4, $7179 ; 32R1-R5: addu $2, $[[T0]], $[[T2]]180 181 ; 32R6-DAG: mul $[[T0:[0-9]+]], $5, $6182 ; 32R6: muhu $[[T1:[0-9]+]], $5, $7183 ; 32R6: addu $[[T0]], $[[T1]], $[[T0]]184 ; 32R6-DAG: mul $[[T2:[0-9]+]], $4, $7185 ; 32R6: addu $2, $[[T0]], $[[T2]]186 ; 32R6-DAG: mul $3, $5, $7187 188 ; M4: dmult $4, $5189 ; M4: mflo $2190 191 ; 64R1-R5: dmult $4, $5192 ; 64R1-R5: mflo $2193 194 ; 64R6: dmul $2, $4, $5195 196 ; MM32R3: multu $[[T0:[0-9]+]], $7197 ; MM32R3: mflo16 $[[T1:[0-9]+]]198 ; MM32R3: mfhi16 $[[T2:[0-9]+]]199 ; MM32R3: mul $[[T0]], $[[T0]], $6200 ; MM32R3: addu16 $2, $[[T2]], $[[T0]]201 ; MM32R3: mul $[[T3:[0-9]+]], $4, $7202 ; MM32R3: addu16 $[[T2]], $[[T2]], $[[T3]]203 204 ; MM32R6: mul $[[T0:[0-9]+]], $5, $6205 ; MM32R6: muhu $[[T1:[0-9]+]], $5, $7206 ; MM32R6: addu16 $[[T2:[0-9]+]], $[[T1]], $[[T0]]207 ; MM32R6: mul $[[T3:[0-9]+]], $4, $7208 ; MM32R6: addu16 $2, $[[T2]], $[[T3]]209 ; MM32R6: mul $[[T1]], $5, $7210 211 %r = mul i64 %a, %b212 ret i64 %r213}214 215define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {216entry:217; ALL-LABEL: mul_i128:218 219 ; GP32-NOT: lw $25, %call16(__multi3)($gp)220 221 ; GP64-NOT-R6: dmult $4, $7222 ; GP64-NOT-R6: mflo $[[T0:[0-9]+]]223 ; GP64-NOT-R6: dmult $5, $6224 ; GP64-NOT-R6: mflo $[[T1:[0-9]+]]225 ; GP64-NOT-R6: dmultu $5, $7226 ; GP64-NOT-R6: mflo $3227 ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]]228 ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]229 ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]230 231 ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6232 ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7233 ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]234 ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7235 ; 64R6: daddu $2, $[[T1]], $[[T0]]236 ; 64R6-DAG: dmul $3, $5, $7237 238 ; MM32-NOT: lw $25, %call16(__multi3)($16)239 240 %r = mul i128 %a, %b241 ret i128 %r242}243