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1; Test all important variants of the 'ret' instruction.2;3; For non-void returns it is necessary to have something to return so we also4; test constant generation here.5;6; We'll test pointer returns in a separate file since the relocation model7; affects it and it's undesirable to repeat the non-pointer returns for each8; relocation model.9 10; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R611; RUN: llc -mtriple=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R612; RUN: llc -mtriple=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R613; RUN: llc -mtriple=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R614; RUN: llc -mtriple=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C15; RUN: llc -mtriple=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R616; RUN: llc -mtriple=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R617; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R618; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R619; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R620 21; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled22; as mthc1 has unmodeled side effects. This is an artifact of our backend.23; Force the delay slot filler off to check that the sequence jr $ra; nop is24; turned into jic 0, $ra.25 26; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C27 28define void @ret_void() {29; ALL-LABEL: ret_void:30 31; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR32; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR33; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC34 35 ret void36}37 38define i8 @ret_i8() {39; ALL-LABEL: ret_i8:40; ALL-DAG: addiu $2, $zero, 341 42; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR43; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR44 45 ret i8 346}47 48define i16 @ret_i16_3() {49; ALL-LABEL: ret_i16_3:50; ALL-DAG: addiu $2, $zero, 351 52; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR53; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR54 55 ret i16 356}57 58define i16 @ret_i16_256() {59; ALL-LABEL: ret_i16_256:60; ALL-DAG: addiu $2, $zero, 25661 62; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR63; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR64 65 ret i16 25666}67 68define i16 @ret_i16_257() {69; ALL-LABEL: ret_i16_257:70; ALL-DAG: addiu $2, $zero, 25771 72; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR73; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR74 75 ret i16 25776}77 78define i32 @ret_i32_257() {79; ALL-LABEL: ret_i32_257:80; ALL-DAG: addiu $2, $zero, 25781 82; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR83; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR84 85 ret i32 25786}87 88define i32 @ret_i32_65536() {89; ALL-LABEL: ret_i32_65536:90; ALL-DAG: lui $2, 191 92; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR93; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR94 95 ret i32 6553696}97 98define i32 @ret_i32_65537() {99; ALL-LABEL: ret_i32_65537:100; ALL: lui $[[T0:[0-9]+]], 1101; ALL-DAG: ori $2, $[[T0]], 1102 103; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR104; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR105 106 ret i32 65537107}108 109define i64 @ret_i64_65537() {110; ALL-LABEL: ret_i64_65537:111; ALL: lui $[[T0:[0-9]+]], 1112 113; GPR32-DAG: ori $3, $[[T0]], 1114; GPR32-DAG: addiu $2, $zero, 0115 116; GPR64-DAG: ori $2, $[[T0]], 1117 118; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR119; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR120 121 ret i64 65537122}123 124define i64 @ret_i64_281479271677952() {125; ALL-LABEL: ret_i64_281479271677952:126; ALL-DAG: lui $[[T0:[0-9]+]], 1127 128; GPR32-DAG: ori $2, $[[T0]], 1129; GPR32-DAG: addiu $3, $zero, 0130 131; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1132; GPR64-DAG: dsll $2, $[[T1]], 32133 134; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR135; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR136 137 ret i64 281479271677952138}139 140define i64 @ret_i64_281479271809026() {141; ALL-LABEL: ret_i64_281479271809026:142; GPR32-DAG: lui $[[T0:[0-9]+]], 1143; GPR32-DAG: lui $[[T1:[0-9]+]], 2144; GPR32-DAG: ori $2, $[[T0]], 1145; GPR32-DAG: ori $3, $[[T1]], 2146 147; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769148; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 16149; GPR64-DAG: daddiu $[[T0:[0-9]+]], $[[T0]], -32767150; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 17151; GPR64-DAG: daddiu $2, $[[T1]], 2152 153; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR154; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR155 156 ret i64 281479271809026157}158 159define float @ret_float_0x0() {160; ALL-LABEL: ret_float_0x0:161 162; NO-MTHC1-DAG: mtc1 $zero, $f0163 164; MTHC1-DAG: mtc1 $zero, $f0165 166; DMTC1-DAG: mtc1 $zero, $f0167 168; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR169; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR170 171 ret float 0x0000000000000000172}173 174define float @ret_float_0x3() {175; ALL-LABEL: ret_float_0x3:176 177; Use a constant pool178; O32-DAG: lwc1 $f0, %lo($CPI179; N64-DAG: lwc1 $f0, %got_ofst($CPI180 181; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR182; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR183; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC184 185; float constants are written as double constants186 ret float 0x36b8000000000000187}188 189define double @ret_double_0x0() {190; ALL-LABEL: ret_double_0x0:191 192; NO-MTHC1-DAG: mtc1 $zero, $f0193; NO-MTHC1-DAG: mtc1 $zero, $f1194 195; MTHC1-DAG: mtc1 $zero, $f0196; MTHC1-DAG: mthc1 $zero, $f0197 198; DMTC1-DAG: dmtc1 $zero, $f0199 200; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR201; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR202; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC203 204 ret double 0x0000000000000000205}206 207define double @ret_double_0x3() {208; ALL-LABEL: ret_double_0x3:209 210; Use a constant pool211; O32-DAG: ldc1 $f0, %lo($CPI212; N64-DAG: ldc1 $f0, %got_ofst($CPI213 214; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR215; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR216; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC217 218 ret double 0x0000000000000003219}220