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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \3; RUN: -check-prefix=MIPS24; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \5; RUN: -check-prefix=MIPS326; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \7; RUN: -check-prefix=MIPS32R28; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \9; RUN: -check-prefix=MIPS32R210; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \11; RUN: -check-prefix=MIPS32R212; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \13; RUN: -check-prefix=MIPS32R614; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \15; RUN: -check-prefix=MIPS316; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \17; RUN: -check-prefix=MIPS418; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \19; RUN: -check-prefix=MIPS6420; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \21; RUN: -check-prefix=MIPS64R222; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \23; RUN: -check-prefix=MIPS64R224; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \25; RUN: -check-prefix=MIPS64R226; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \27; RUN: -check-prefix=MIPS64R628; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \29; RUN: -check-prefix=MMR330; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \31; RUN: -check-prefix=MMR632 33define signext i1 @shl_i1(i1 signext %a, i1 signext %b) {34; MIPS2-LABEL: shl_i1:35; MIPS2: # %bb.0: # %entry36; MIPS2-NEXT: jr $ra37; MIPS2-NEXT: move $2, $438;39; MIPS32-LABEL: shl_i1:40; MIPS32: # %bb.0: # %entry41; MIPS32-NEXT: jr $ra42; MIPS32-NEXT: move $2, $443;44; MIPS32R2-LABEL: shl_i1:45; MIPS32R2: # %bb.0: # %entry46; MIPS32R2-NEXT: jr $ra47; MIPS32R2-NEXT: move $2, $448;49; MIPS32R6-LABEL: shl_i1:50; MIPS32R6: # %bb.0: # %entry51; MIPS32R6-NEXT: jr $ra52; MIPS32R6-NEXT: move $2, $453;54; MIPS3-LABEL: shl_i1:55; MIPS3: # %bb.0: # %entry56; MIPS3-NEXT: jr $ra57; MIPS3-NEXT: move $2, $458;59; MIPS4-LABEL: shl_i1:60; MIPS4: # %bb.0: # %entry61; MIPS4-NEXT: jr $ra62; MIPS4-NEXT: move $2, $463;64; MIPS64-LABEL: shl_i1:65; MIPS64: # %bb.0: # %entry66; MIPS64-NEXT: jr $ra67; MIPS64-NEXT: move $2, $468;69; MIPS64R2-LABEL: shl_i1:70; MIPS64R2: # %bb.0: # %entry71; MIPS64R2-NEXT: jr $ra72; MIPS64R2-NEXT: move $2, $473;74; MIPS64R6-LABEL: shl_i1:75; MIPS64R6: # %bb.0: # %entry76; MIPS64R6-NEXT: jr $ra77; MIPS64R6-NEXT: move $2, $478;79; MMR3-LABEL: shl_i1:80; MMR3: # %bb.0: # %entry81; MMR3-NEXT: move $2, $482; MMR3-NEXT: jrc $ra83;84; MMR6-LABEL: shl_i1:85; MMR6: # %bb.0: # %entry86; MMR6-NEXT: move $2, $487; MMR6-NEXT: jrc $ra88entry:89 90 %r = shl i1 %a, %b91 ret i1 %r92}93 94define signext i8 @shl_i8(i8 signext %a, i8 signext %b) {95; MIPS2-LABEL: shl_i8:96; MIPS2: # %bb.0: # %entry97; MIPS2-NEXT: sllv $1, $4, $598; MIPS2-NEXT: sll $1, $1, 2499; MIPS2-NEXT: jr $ra100; MIPS2-NEXT: sra $2, $1, 24101;102; MIPS32-LABEL: shl_i8:103; MIPS32: # %bb.0: # %entry104; MIPS32-NEXT: sllv $1, $4, $5105; MIPS32-NEXT: sll $1, $1, 24106; MIPS32-NEXT: jr $ra107; MIPS32-NEXT: sra $2, $1, 24108;109; MIPS32R2-LABEL: shl_i8:110; MIPS32R2: # %bb.0: # %entry111; MIPS32R2-NEXT: sllv $1, $4, $5112; MIPS32R2-NEXT: jr $ra113; MIPS32R2-NEXT: seb $2, $1114;115; MIPS32R6-LABEL: shl_i8:116; MIPS32R6: # %bb.0: # %entry117; MIPS32R6-NEXT: sllv $1, $4, $5118; MIPS32R6-NEXT: jr $ra119; MIPS32R6-NEXT: seb $2, $1120;121; MIPS3-LABEL: shl_i8:122; MIPS3: # %bb.0: # %entry123; MIPS3-NEXT: sllv $1, $4, $5124; MIPS3-NEXT: sll $1, $1, 24125; MIPS3-NEXT: jr $ra126; MIPS3-NEXT: sra $2, $1, 24127;128; MIPS4-LABEL: shl_i8:129; MIPS4: # %bb.0: # %entry130; MIPS4-NEXT: sllv $1, $4, $5131; MIPS4-NEXT: sll $1, $1, 24132; MIPS4-NEXT: jr $ra133; MIPS4-NEXT: sra $2, $1, 24134;135; MIPS64-LABEL: shl_i8:136; MIPS64: # %bb.0: # %entry137; MIPS64-NEXT: sllv $1, $4, $5138; MIPS64-NEXT: sll $1, $1, 24139; MIPS64-NEXT: jr $ra140; MIPS64-NEXT: sra $2, $1, 24141;142; MIPS64R2-LABEL: shl_i8:143; MIPS64R2: # %bb.0: # %entry144; MIPS64R2-NEXT: sllv $1, $4, $5145; MIPS64R2-NEXT: jr $ra146; MIPS64R2-NEXT: seb $2, $1147;148; MIPS64R6-LABEL: shl_i8:149; MIPS64R6: # %bb.0: # %entry150; MIPS64R6-NEXT: sllv $1, $4, $5151; MIPS64R6-NEXT: jr $ra152; MIPS64R6-NEXT: seb $2, $1153;154; MMR3-LABEL: shl_i8:155; MMR3: # %bb.0: # %entry156; MMR3-NEXT: andi16 $2, $5, 255157; MMR3-NEXT: sllv $1, $4, $2158; MMR3-NEXT: jr $ra159; MMR3-NEXT: seb $2, $1160;161; MMR6-LABEL: shl_i8:162; MMR6: # %bb.0: # %entry163; MMR6-NEXT: andi16 $2, $5, 255164; MMR6-NEXT: sllv $1, $4, $2165; MMR6-NEXT: seb $2, $1166; MMR6-NEXT: jrc $ra167entry:168 169 %r = shl i8 %a, %b170 ret i8 %r171}172 173define signext i16 @shl_i16(i16 signext %a, i16 signext %b) {174; MIPS2-LABEL: shl_i16:175; MIPS2: # %bb.0: # %entry176; MIPS2-NEXT: sllv $1, $4, $5177; MIPS2-NEXT: sll $1, $1, 16178; MIPS2-NEXT: jr $ra179; MIPS2-NEXT: sra $2, $1, 16180;181; MIPS32-LABEL: shl_i16:182; MIPS32: # %bb.0: # %entry183; MIPS32-NEXT: sllv $1, $4, $5184; MIPS32-NEXT: sll $1, $1, 16185; MIPS32-NEXT: jr $ra186; MIPS32-NEXT: sra $2, $1, 16187;188; MIPS32R2-LABEL: shl_i16:189; MIPS32R2: # %bb.0: # %entry190; MIPS32R2-NEXT: sllv $1, $4, $5191; MIPS32R2-NEXT: jr $ra192; MIPS32R2-NEXT: seh $2, $1193;194; MIPS32R6-LABEL: shl_i16:195; MIPS32R6: # %bb.0: # %entry196; MIPS32R6-NEXT: sllv $1, $4, $5197; MIPS32R6-NEXT: jr $ra198; MIPS32R6-NEXT: seh $2, $1199;200; MIPS3-LABEL: shl_i16:201; MIPS3: # %bb.0: # %entry202; MIPS3-NEXT: sllv $1, $4, $5203; MIPS3-NEXT: sll $1, $1, 16204; MIPS3-NEXT: jr $ra205; MIPS3-NEXT: sra $2, $1, 16206;207; MIPS4-LABEL: shl_i16:208; MIPS4: # %bb.0: # %entry209; MIPS4-NEXT: sllv $1, $4, $5210; MIPS4-NEXT: sll $1, $1, 16211; MIPS4-NEXT: jr $ra212; MIPS4-NEXT: sra $2, $1, 16213;214; MIPS64-LABEL: shl_i16:215; MIPS64: # %bb.0: # %entry216; MIPS64-NEXT: sllv $1, $4, $5217; MIPS64-NEXT: sll $1, $1, 16218; MIPS64-NEXT: jr $ra219; MIPS64-NEXT: sra $2, $1, 16220;221; MIPS64R2-LABEL: shl_i16:222; MIPS64R2: # %bb.0: # %entry223; MIPS64R2-NEXT: sllv $1, $4, $5224; MIPS64R2-NEXT: jr $ra225; MIPS64R2-NEXT: seh $2, $1226;227; MIPS64R6-LABEL: shl_i16:228; MIPS64R6: # %bb.0: # %entry229; MIPS64R6-NEXT: sllv $1, $4, $5230; MIPS64R6-NEXT: jr $ra231; MIPS64R6-NEXT: seh $2, $1232;233; MMR3-LABEL: shl_i16:234; MMR3: # %bb.0: # %entry235; MMR3-NEXT: andi16 $2, $5, 65535236; MMR3-NEXT: sllv $1, $4, $2237; MMR3-NEXT: jr $ra238; MMR3-NEXT: seh $2, $1239;240; MMR6-LABEL: shl_i16:241; MMR6: # %bb.0: # %entry242; MMR6-NEXT: andi16 $2, $5, 65535243; MMR6-NEXT: sllv $1, $4, $2244; MMR6-NEXT: seh $2, $1245; MMR6-NEXT: jrc $ra246entry:247 248 %r = shl i16 %a, %b249 ret i16 %r250}251 252define signext i32 @shl_i32(i32 signext %a, i32 signext %b) {253; MIPS2-LABEL: shl_i32:254; MIPS2: # %bb.0: # %entry255; MIPS2-NEXT: jr $ra256; MIPS2-NEXT: sllv $2, $4, $5257;258; MIPS32-LABEL: shl_i32:259; MIPS32: # %bb.0: # %entry260; MIPS32-NEXT: jr $ra261; MIPS32-NEXT: sllv $2, $4, $5262;263; MIPS32R2-LABEL: shl_i32:264; MIPS32R2: # %bb.0: # %entry265; MIPS32R2-NEXT: jr $ra266; MIPS32R2-NEXT: sllv $2, $4, $5267;268; MIPS32R6-LABEL: shl_i32:269; MIPS32R6: # %bb.0: # %entry270; MIPS32R6-NEXT: jr $ra271; MIPS32R6-NEXT: sllv $2, $4, $5272;273; MIPS3-LABEL: shl_i32:274; MIPS3: # %bb.0: # %entry275; MIPS3-NEXT: jr $ra276; MIPS3-NEXT: sllv $2, $4, $5277;278; MIPS4-LABEL: shl_i32:279; MIPS4: # %bb.0: # %entry280; MIPS4-NEXT: jr $ra281; MIPS4-NEXT: sllv $2, $4, $5282;283; MIPS64-LABEL: shl_i32:284; MIPS64: # %bb.0: # %entry285; MIPS64-NEXT: jr $ra286; MIPS64-NEXT: sllv $2, $4, $5287;288; MIPS64R2-LABEL: shl_i32:289; MIPS64R2: # %bb.0: # %entry290; MIPS64R2-NEXT: jr $ra291; MIPS64R2-NEXT: sllv $2, $4, $5292;293; MIPS64R6-LABEL: shl_i32:294; MIPS64R6: # %bb.0: # %entry295; MIPS64R6-NEXT: jr $ra296; MIPS64R6-NEXT: sllv $2, $4, $5297;298; MMR3-LABEL: shl_i32:299; MMR3: # %bb.0: # %entry300; MMR3-NEXT: jr $ra301; MMR3-NEXT: sllv $2, $4, $5302;303; MMR6-LABEL: shl_i32:304; MMR6: # %bb.0: # %entry305; MMR6-NEXT: sllv $2, $4, $5306; MMR6-NEXT: jrc $ra307entry:308 309 %r = shl i32 %a, %b310 ret i32 %r311}312 313define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {314; MIPS2-LABEL: shl_i64:315; MIPS2: # %bb.0: # %entry316; MIPS2-NEXT: sllv $6, $5, $7317; MIPS2-NEXT: andi $8, $7, 32318; MIPS2-NEXT: beqz $8, $BB4_3319; MIPS2-NEXT: move $2, $6320; MIPS2-NEXT: # %bb.1: # %entry321; MIPS2-NEXT: beqz $8, $BB4_4322; MIPS2-NEXT: addiu $3, $zero, 0323; MIPS2-NEXT: $BB4_2: # %entry324; MIPS2-NEXT: jr $ra325; MIPS2-NEXT: nop326; MIPS2-NEXT: $BB4_3: # %entry327; MIPS2-NEXT: sllv $1, $4, $7328; MIPS2-NEXT: xori $2, $7, 31329; MIPS2-NEXT: srl $3, $5, 1330; MIPS2-NEXT: srlv $2, $3, $2331; MIPS2-NEXT: or $2, $1, $2332; MIPS2-NEXT: bnez $8, $BB4_2333; MIPS2-NEXT: addiu $3, $zero, 0334; MIPS2-NEXT: $BB4_4: # %entry335; MIPS2-NEXT: jr $ra336; MIPS2-NEXT: move $3, $6337;338; MIPS32-LABEL: shl_i64:339; MIPS32: # %bb.0: # %entry340; MIPS32-NEXT: sllv $1, $4, $7341; MIPS32-NEXT: xori $2, $7, 31342; MIPS32-NEXT: srl $3, $5, 1343; MIPS32-NEXT: srlv $2, $3, $2344; MIPS32-NEXT: or $2, $1, $2345; MIPS32-NEXT: sllv $3, $5, $7346; MIPS32-NEXT: andi $1, $7, 32347; MIPS32-NEXT: movn $2, $3, $1348; MIPS32-NEXT: jr $ra349; MIPS32-NEXT: movn $3, $zero, $1350;351; MIPS32R2-LABEL: shl_i64:352; MIPS32R2: # %bb.0: # %entry353; MIPS32R2-NEXT: sllv $1, $4, $7354; MIPS32R2-NEXT: xori $2, $7, 31355; MIPS32R2-NEXT: srl $3, $5, 1356; MIPS32R2-NEXT: srlv $2, $3, $2357; MIPS32R2-NEXT: or $2, $1, $2358; MIPS32R2-NEXT: sllv $3, $5, $7359; MIPS32R2-NEXT: andi $1, $7, 32360; MIPS32R2-NEXT: movn $2, $3, $1361; MIPS32R2-NEXT: jr $ra362; MIPS32R2-NEXT: movn $3, $zero, $1363;364; MIPS32R6-LABEL: shl_i64:365; MIPS32R6: # %bb.0: # %entry366; MIPS32R6-NEXT: sllv $1, $4, $7367; MIPS32R6-NEXT: xori $2, $7, 31368; MIPS32R6-NEXT: srl $3, $5, 1369; MIPS32R6-NEXT: srlv $2, $3, $2370; MIPS32R6-NEXT: or $1, $1, $2371; MIPS32R6-NEXT: andi $3, $7, 32372; MIPS32R6-NEXT: seleqz $1, $1, $3373; MIPS32R6-NEXT: sllv $4, $5, $7374; MIPS32R6-NEXT: selnez $2, $4, $3375; MIPS32R6-NEXT: or $2, $2, $1376; MIPS32R6-NEXT: jr $ra377; MIPS32R6-NEXT: seleqz $3, $4, $3378;379; MIPS3-LABEL: shl_i64:380; MIPS3: # %bb.0: # %entry381; MIPS3-NEXT: jr $ra382; MIPS3-NEXT: dsllv $2, $4, $5383;384; MIPS4-LABEL: shl_i64:385; MIPS4: # %bb.0: # %entry386; MIPS4-NEXT: jr $ra387; MIPS4-NEXT: dsllv $2, $4, $5388;389; MIPS64-LABEL: shl_i64:390; MIPS64: # %bb.0: # %entry391; MIPS64-NEXT: jr $ra392; MIPS64-NEXT: dsllv $2, $4, $5393;394; MIPS64R2-LABEL: shl_i64:395; MIPS64R2: # %bb.0: # %entry396; MIPS64R2-NEXT: jr $ra397; MIPS64R2-NEXT: dsllv $2, $4, $5398;399; MIPS64R6-LABEL: shl_i64:400; MIPS64R6: # %bb.0: # %entry401; MIPS64R6-NEXT: jr $ra402; MIPS64R6-NEXT: dsllv $2, $4, $5403;404; MMR3-LABEL: shl_i64:405; MMR3: # %bb.0: # %entry406; MMR3-NEXT: sllv $3, $4, $7407; MMR3-NEXT: xori $1, $7, 31408; MMR3-NEXT: srl16 $2, $5, 1409; MMR3-NEXT: srlv $2, $2, $1410; MMR3-NEXT: or16 $2, $3411; MMR3-NEXT: sllv $3, $5, $7412; MMR3-NEXT: andi16 $4, $7, 32413; MMR3-NEXT: movn $2, $3, $4414; MMR3-NEXT: li16 $5, 0415; MMR3-NEXT: jr $ra416; MMR3-NEXT: movn $3, $5, $4417;418; MMR6-LABEL: shl_i64:419; MMR6: # %bb.0: # %entry420; MMR6-NEXT: sllv $1, $4, $7421; MMR6-NEXT: xori $2, $7, 31422; MMR6-NEXT: srl16 $3, $5, 1423; MMR6-NEXT: srlv $2, $3, $2424; MMR6-NEXT: or $1, $1, $2425; MMR6-NEXT: andi16 $3, $7, 32426; MMR6-NEXT: seleqz $1, $1, $3427; MMR6-NEXT: sllv $4, $5, $7428; MMR6-NEXT: selnez $2, $4, $3429; MMR6-NEXT: or $2, $2, $1430; MMR6-NEXT: seleqz $3, $4, $3431; MMR6-NEXT: jrc $ra432entry:433 434 %r = shl i64 %a, %b435 ret i64 %r436}437 438define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {439; MIPS2-LABEL: shl_i128:440; MIPS2: # %bb.0: # %entry441; MIPS2-NEXT: addiu $sp, $sp, -32442; MIPS2-NEXT: .cfi_def_cfa_offset 32443; MIPS2-NEXT: lw $1, 60($sp)444; MIPS2-NEXT: srl $2, $1, 3445; MIPS2-NEXT: sw $7, 12($sp)446; MIPS2-NEXT: sw $6, 8($sp)447; MIPS2-NEXT: sw $5, 4($sp)448; MIPS2-NEXT: sw $4, 0($sp)449; MIPS2-NEXT: andi $2, $2, 12450; MIPS2-NEXT: addiu $3, $sp, 0451; MIPS2-NEXT: addu $4, $3, $2452; MIPS2-NEXT: sw $zero, 28($sp)453; MIPS2-NEXT: sw $zero, 24($sp)454; MIPS2-NEXT: sw $zero, 20($sp)455; MIPS2-NEXT: sw $zero, 16($sp)456; MIPS2-NEXT: lw $5, 8($4)457; MIPS2-NEXT: lw $2, 4($4)458; MIPS2-NEXT: sllv $3, $2, $1459; MIPS2-NEXT: srl $6, $5, 1460; MIPS2-NEXT: andi $7, $1, 31461; MIPS2-NEXT: xori $7, $7, 31462; MIPS2-NEXT: srlv $6, $6, $7463; MIPS2-NEXT: lw $8, 0($4)464; MIPS2-NEXT: sllv $8, $8, $1465; MIPS2-NEXT: srl $2, $2, 1466; MIPS2-NEXT: srlv $2, $2, $7467; MIPS2-NEXT: or $2, $8, $2468; MIPS2-NEXT: or $3, $3, $6469; MIPS2-NEXT: sllv $5, $5, $1470; MIPS2-NEXT: lw $6, 12($4)471; MIPS2-NEXT: srl $4, $6, 1472; MIPS2-NEXT: srlv $4, $4, $7473; MIPS2-NEXT: or $4, $5, $4474; MIPS2-NEXT: sllv $5, $6, $1475; MIPS2-NEXT: jr $ra476; MIPS2-NEXT: addiu $sp, $sp, 32477;478; MIPS32-LABEL: shl_i128:479; MIPS32: # %bb.0: # %entry480; MIPS32-NEXT: addiu $sp, $sp, -32481; MIPS32-NEXT: .cfi_def_cfa_offset 32482; MIPS32-NEXT: lw $1, 60($sp)483; MIPS32-NEXT: srl $2, $1, 3484; MIPS32-NEXT: sw $7, 12($sp)485; MIPS32-NEXT: sw $6, 8($sp)486; MIPS32-NEXT: sw $5, 4($sp)487; MIPS32-NEXT: sw $4, 0($sp)488; MIPS32-NEXT: andi $2, $2, 12489; MIPS32-NEXT: addiu $3, $sp, 0490; MIPS32-NEXT: addu $4, $3, $2491; MIPS32-NEXT: sw $zero, 28($sp)492; MIPS32-NEXT: sw $zero, 24($sp)493; MIPS32-NEXT: sw $zero, 20($sp)494; MIPS32-NEXT: sw $zero, 16($sp)495; MIPS32-NEXT: lw $5, 8($4)496; MIPS32-NEXT: lw $2, 4($4)497; MIPS32-NEXT: sllv $3, $2, $1498; MIPS32-NEXT: srl $6, $5, 1499; MIPS32-NEXT: andi $7, $1, 31500; MIPS32-NEXT: xori $7, $7, 31501; MIPS32-NEXT: srlv $6, $6, $7502; MIPS32-NEXT: lw $8, 0($4)503; MIPS32-NEXT: sllv $8, $8, $1504; MIPS32-NEXT: srl $2, $2, 1505; MIPS32-NEXT: srlv $2, $2, $7506; MIPS32-NEXT: or $2, $8, $2507; MIPS32-NEXT: or $3, $3, $6508; MIPS32-NEXT: sllv $5, $5, $1509; MIPS32-NEXT: lw $6, 12($4)510; MIPS32-NEXT: srl $4, $6, 1511; MIPS32-NEXT: srlv $4, $4, $7512; MIPS32-NEXT: or $4, $5, $4513; MIPS32-NEXT: sllv $5, $6, $1514; MIPS32-NEXT: jr $ra515; MIPS32-NEXT: addiu $sp, $sp, 32516;517; MIPS32R2-LABEL: shl_i128:518; MIPS32R2: # %bb.0: # %entry519; MIPS32R2-NEXT: addiu $sp, $sp, -32520; MIPS32R2-NEXT: .cfi_def_cfa_offset 32521; MIPS32R2-NEXT: lw $1, 60($sp)522; MIPS32R2-NEXT: srl $2, $1, 3523; MIPS32R2-NEXT: sw $7, 12($sp)524; MIPS32R2-NEXT: sw $6, 8($sp)525; MIPS32R2-NEXT: sw $5, 4($sp)526; MIPS32R2-NEXT: sw $4, 0($sp)527; MIPS32R2-NEXT: andi $2, $2, 12528; MIPS32R2-NEXT: addiu $3, $sp, 0529; MIPS32R2-NEXT: addu $4, $3, $2530; MIPS32R2-NEXT: sw $zero, 28($sp)531; MIPS32R2-NEXT: sw $zero, 24($sp)532; MIPS32R2-NEXT: sw $zero, 20($sp)533; MIPS32R2-NEXT: sw $zero, 16($sp)534; MIPS32R2-NEXT: lw $5, 8($4)535; MIPS32R2-NEXT: lw $2, 4($4)536; MIPS32R2-NEXT: sllv $3, $2, $1537; MIPS32R2-NEXT: srl $6, $5, 1538; MIPS32R2-NEXT: andi $7, $1, 31539; MIPS32R2-NEXT: xori $7, $7, 31540; MIPS32R2-NEXT: srlv $6, $6, $7541; MIPS32R2-NEXT: lw $8, 0($4)542; MIPS32R2-NEXT: sllv $8, $8, $1543; MIPS32R2-NEXT: srl $2, $2, 1544; MIPS32R2-NEXT: srlv $2, $2, $7545; MIPS32R2-NEXT: or $2, $8, $2546; MIPS32R2-NEXT: or $3, $3, $6547; MIPS32R2-NEXT: sllv $5, $5, $1548; MIPS32R2-NEXT: lw $6, 12($4)549; MIPS32R2-NEXT: srl $4, $6, 1550; MIPS32R2-NEXT: srlv $4, $4, $7551; MIPS32R2-NEXT: or $4, $5, $4552; MIPS32R2-NEXT: sllv $5, $6, $1553; MIPS32R2-NEXT: jr $ra554; MIPS32R2-NEXT: addiu $sp, $sp, 32555;556; MIPS32R6-LABEL: shl_i128:557; MIPS32R6: # %bb.0: # %entry558; MIPS32R6-NEXT: addiu $sp, $sp, -32559; MIPS32R6-NEXT: .cfi_def_cfa_offset 32560; MIPS32R6-NEXT: lw $1, 60($sp)561; MIPS32R6-NEXT: srl $2, $1, 3562; MIPS32R6-NEXT: sw $7, 12($sp)563; MIPS32R6-NEXT: sw $6, 8($sp)564; MIPS32R6-NEXT: sw $5, 4($sp)565; MIPS32R6-NEXT: sw $4, 0($sp)566; MIPS32R6-NEXT: andi $2, $2, 12567; MIPS32R6-NEXT: addiu $3, $sp, 0568; MIPS32R6-NEXT: addu $4, $3, $2569; MIPS32R6-NEXT: sw $zero, 28($sp)570; MIPS32R6-NEXT: sw $zero, 24($sp)571; MIPS32R6-NEXT: sw $zero, 20($sp)572; MIPS32R6-NEXT: sw $zero, 16($sp)573; MIPS32R6-NEXT: lw $5, 8($4)574; MIPS32R6-NEXT: lw $2, 4($4)575; MIPS32R6-NEXT: sllv $3, $2, $1576; MIPS32R6-NEXT: srl $6, $5, 1577; MIPS32R6-NEXT: andi $7, $1, 31578; MIPS32R6-NEXT: xori $7, $7, 31579; MIPS32R6-NEXT: srlv $6, $6, $7580; MIPS32R6-NEXT: lw $8, 0($4)581; MIPS32R6-NEXT: sllv $8, $8, $1582; MIPS32R6-NEXT: srl $2, $2, 1583; MIPS32R6-NEXT: srlv $2, $2, $7584; MIPS32R6-NEXT: or $2, $8, $2585; MIPS32R6-NEXT: or $3, $3, $6586; MIPS32R6-NEXT: sllv $5, $5, $1587; MIPS32R6-NEXT: lw $6, 12($4)588; MIPS32R6-NEXT: srl $4, $6, 1589; MIPS32R6-NEXT: srlv $4, $4, $7590; MIPS32R6-NEXT: or $4, $5, $4591; MIPS32R6-NEXT: sllv $5, $6, $1592; MIPS32R6-NEXT: jr $ra593; MIPS32R6-NEXT: addiu $sp, $sp, 32594;595; MIPS3-LABEL: shl_i128:596; MIPS3: # %bb.0: # %entry597; MIPS3-NEXT: sll $3, $7, 0598; MIPS3-NEXT: dsllv $6, $5, $7599; MIPS3-NEXT: andi $8, $3, 64600; MIPS3-NEXT: beqz $8, .LBB5_3601; MIPS3-NEXT: move $2, $6602; MIPS3-NEXT: # %bb.1: # %entry603; MIPS3-NEXT: beqz $8, .LBB5_4604; MIPS3-NEXT: daddiu $3, $zero, 0605; MIPS3-NEXT: .LBB5_2: # %entry606; MIPS3-NEXT: jr $ra607; MIPS3-NEXT: nop608; MIPS3-NEXT: .LBB5_3: # %entry609; MIPS3-NEXT: dsllv $1, $4, $7610; MIPS3-NEXT: dsrl $2, $5, 1611; MIPS3-NEXT: xori $3, $3, 63612; MIPS3-NEXT: dsrlv $2, $2, $3613; MIPS3-NEXT: or $2, $1, $2614; MIPS3-NEXT: bnez $8, .LBB5_2615; MIPS3-NEXT: daddiu $3, $zero, 0616; MIPS3-NEXT: .LBB5_4: # %entry617; MIPS3-NEXT: jr $ra618; MIPS3-NEXT: move $3, $6619;620; MIPS4-LABEL: shl_i128:621; MIPS4: # %bb.0: # %entry622; MIPS4-NEXT: dsllv $1, $4, $7623; MIPS4-NEXT: dsrl $2, $5, 1624; MIPS4-NEXT: sll $4, $7, 0625; MIPS4-NEXT: xori $3, $4, 63626; MIPS4-NEXT: dsrlv $2, $2, $3627; MIPS4-NEXT: or $2, $1, $2628; MIPS4-NEXT: dsllv $3, $5, $7629; MIPS4-NEXT: andi $1, $4, 64630; MIPS4-NEXT: movn $2, $3, $1631; MIPS4-NEXT: jr $ra632; MIPS4-NEXT: movn $3, $zero, $1633;634; MIPS64-LABEL: shl_i128:635; MIPS64: # %bb.0: # %entry636; MIPS64-NEXT: dsllv $1, $4, $7637; MIPS64-NEXT: dsrl $2, $5, 1638; MIPS64-NEXT: sll $4, $7, 0639; MIPS64-NEXT: xori $3, $4, 63640; MIPS64-NEXT: dsrlv $2, $2, $3641; MIPS64-NEXT: or $2, $1, $2642; MIPS64-NEXT: dsllv $3, $5, $7643; MIPS64-NEXT: andi $1, $4, 64644; MIPS64-NEXT: movn $2, $3, $1645; MIPS64-NEXT: jr $ra646; MIPS64-NEXT: movn $3, $zero, $1647;648; MIPS64R2-LABEL: shl_i128:649; MIPS64R2: # %bb.0: # %entry650; MIPS64R2-NEXT: dsllv $1, $4, $7651; MIPS64R2-NEXT: dsrl $2, $5, 1652; MIPS64R2-NEXT: sll $4, $7, 0653; MIPS64R2-NEXT: xori $3, $4, 63654; MIPS64R2-NEXT: dsrlv $2, $2, $3655; MIPS64R2-NEXT: or $2, $1, $2656; MIPS64R2-NEXT: dsllv $3, $5, $7657; MIPS64R2-NEXT: andi $1, $4, 64658; MIPS64R2-NEXT: movn $2, $3, $1659; MIPS64R2-NEXT: jr $ra660; MIPS64R2-NEXT: movn $3, $zero, $1661;662; MIPS64R6-LABEL: shl_i128:663; MIPS64R6: # %bb.0: # %entry664; MIPS64R6-NEXT: dsllv $1, $4, $7665; MIPS64R6-NEXT: dsrl $2, $5, 1666; MIPS64R6-NEXT: sll $3, $7, 0667; MIPS64R6-NEXT: xori $4, $3, 63668; MIPS64R6-NEXT: dsrlv $2, $2, $4669; MIPS64R6-NEXT: or $1, $1, $2670; MIPS64R6-NEXT: andi $2, $3, 64671; MIPS64R6-NEXT: sll $3, $2, 0672; MIPS64R6-NEXT: seleqz $1, $1, $3673; MIPS64R6-NEXT: dsllv $4, $5, $7674; MIPS64R6-NEXT: selnez $2, $4, $3675; MIPS64R6-NEXT: or $2, $2, $1676; MIPS64R6-NEXT: jr $ra677; MIPS64R6-NEXT: seleqz $3, $4, $3678;679; MMR3-LABEL: shl_i128:680; MMR3: # %bb.0: # %entry681; MMR3-NEXT: addiusp -40682; MMR3-NEXT: .cfi_def_cfa_offset 40683; MMR3-NEXT: swp $16, 32($sp)684; MMR3-NEXT: .cfi_offset 17, -4685; MMR3-NEXT: .cfi_offset 16, -8686; MMR3-NEXT: li16 $2, 0687; MMR3-NEXT: sw $2, 28($sp)688; MMR3-NEXT: sw $2, 24($sp)689; MMR3-NEXT: sw $2, 20($sp)690; MMR3-NEXT: sw $2, 16($sp)691; MMR3-NEXT: swp $6, 8($sp)692; MMR3-NEXT: swp $4, 0($sp)693; MMR3-NEXT: lw $2, 68($sp)694; MMR3-NEXT: srl16 $3, $2, 3695; MMR3-NEXT: andi $3, $3, 12696; MMR3-NEXT: addiur1sp $4, 0697; MMR3-NEXT: addu16 $4, $4, $3698; MMR3-NEXT: lw16 $6, 8($4)699; MMR3-NEXT: lw16 $7, 4($4)700; MMR3-NEXT: andi16 $5, $2, 31701; MMR3-NEXT: sllv $16, $7, $5702; MMR3-NEXT: srl16 $2, $6, 1703; MMR3-NEXT: xori $1, $5, 31704; MMR3-NEXT: srlv $3, $2, $1705; MMR3-NEXT: lw16 $2, 0($4)706; MMR3-NEXT: sllv $17, $2, $5707; MMR3-NEXT: srl16 $2, $7, 1708; MMR3-NEXT: srlv $2, $2, $1709; MMR3-NEXT: or16 $2, $17710; MMR3-NEXT: or16 $3, $16711; MMR3-NEXT: sllv $6, $6, $5712; MMR3-NEXT: lw16 $7, 12($4)713; MMR3-NEXT: srl16 $4, $7, 1714; MMR3-NEXT: srlv $4, $4, $1715; MMR3-NEXT: or16 $4, $6716; MMR3-NEXT: sllv $5, $7, $5717; MMR3-NEXT: lwp $16, 32($sp)718; MMR3-NEXT: addiusp 40719; MMR3-NEXT: jrc $ra720;721; MMR6-LABEL: shl_i128:722; MMR6: # %bb.0: # %entry723; MMR6-NEXT: addiu $sp, $sp, -32724; MMR6-NEXT: .cfi_def_cfa_offset 32725; MMR6-NEXT: li16 $2, 0726; MMR6-NEXT: sw $2, 28($sp)727; MMR6-NEXT: sw $2, 24($sp)728; MMR6-NEXT: sw $2, 20($sp)729; MMR6-NEXT: sw $2, 16($sp)730; MMR6-NEXT: sw $7, 12($sp)731; MMR6-NEXT: sw $6, 8($sp)732; MMR6-NEXT: sw $5, 4($sp)733; MMR6-NEXT: sw $4, 0($sp)734; MMR6-NEXT: lw $2, 60($sp)735; MMR6-NEXT: srl16 $3, $2, 3736; MMR6-NEXT: andi $3, $3, 12737; MMR6-NEXT: addiu $4, $sp, 0738; MMR6-NEXT: addu16 $4, $4, $3739; MMR6-NEXT: lw16 $5, 8($4)740; MMR6-NEXT: lw16 $3, 4($4)741; MMR6-NEXT: andi16 $6, $2, 31742; MMR6-NEXT: sllv $1, $3, $6743; MMR6-NEXT: srl16 $2, $5, 1744; MMR6-NEXT: xori $7, $6, 31745; MMR6-NEXT: srlv $8, $2, $7746; MMR6-NEXT: lw16 $2, 0($4)747; MMR6-NEXT: sllv $2, $2, $6748; MMR6-NEXT: srl16 $3, $3, 1749; MMR6-NEXT: srlv $3, $3, $7750; MMR6-NEXT: or $2, $2, $3751; MMR6-NEXT: or $3, $1, $8752; MMR6-NEXT: sllv $1, $5, $6753; MMR6-NEXT: lw16 $5, 12($4)754; MMR6-NEXT: srl16 $4, $5, 1755; MMR6-NEXT: srlv $4, $4, $7756; MMR6-NEXT: or $4, $1, $4757; MMR6-NEXT: sllv $5, $5, $6758; MMR6-NEXT: addiu $sp, $sp, 32759; MMR6-NEXT: jrc $ra760entry:761 762; o32 shouldn't use TImode helpers.763; GP32-NOT: lw $25, %call16(__ashlti3)($gp)764; MM-NOT: lw $25, %call16(__ashlti3)($2)765 766 %r = shl i128 %a, %b767 ret i128 %r768}769