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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS323; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR34; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R65; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR66; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS47; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R68; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips,+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MMR5FP649; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r5 -mattr=+fp64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R5FP64310 11; Test subword and word stores. We use -asm-show-inst to test that the produced12; instructions match the expected ISA.13 14; NOTE: As the -asm-show-inst shows the internal numbering of instructions15; and registers, these numbers have been replaced with wildcard regexes.16 17@a = common global i8 0, align 418@b = common global i16 0, align 419@c = common global i32 0, align 420@d = common global i64 0, align 821@e = common global float 0.0, align 422@f = common global double 0.0, align 823 24define void @f1(i8 %a) {25; MIPS32-LABEL: f1:26; MIPS32: # %bb.0:27; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi28; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1:]]>29; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,a)>>30; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR31; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>32; MIPS32-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB33; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3:]]>34; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>35; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,a)>>36;37; MMR3-LABEL: f1:38; MMR3: # %bb.0:39; MMR3-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM40; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1:]]>41; MMR3-NEXT: # <MCOperand Expr:specifier(4024,a)>>42; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM43; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>44; MMR3-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM45; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3:]]>46; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>47; MMR3-NEXT: # <MCOperand Expr:specifier(4027,a)>>48;49; MIPS32R6-LABEL: f1:50; MIPS32R6: # %bb.0:51; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi52; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>53; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,a)>>54; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7:]] JALR55; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4:]]>56; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>57; MIPS32R6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB58; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>59; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>60; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,a)>>61;62; MMR6-LABEL: f1:63; MMR6: # %bb.0:64; MMR6-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM65; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1:]]>66; MMR6-NEXT: # <MCOperand Expr:specifier(4024,a)>>67; MMR6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM68; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3:]]>69; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>70; MMR6-NEXT: # <MCOperand Expr:specifier(4027,a)>>71; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM72; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>73;74; MIPS4-LABEL: f1:75; MIPS4: # %bb.0:76; MIPS4-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi6477; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5:]]>78; MIPS4-NEXT: # <MCOperand Expr:specifier(4026,a)>>79; MIPS4-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu80; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>81; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>82; MIPS4-NEXT: # <MCOperand Expr:specifier(4025,a)>>83; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL84; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>85; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>86; MIPS4-NEXT: # <MCOperand Imm:16>>87; MIPS4-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu88; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>89; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>90; MIPS4-NEXT: # <MCOperand Expr:specifier(4024,a)>>91; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL92; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>93; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>94; MIPS4-NEXT: # <MCOperand Imm:16>>95; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR96; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>97; MIPS4-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST12:]] SB6498; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG7:]]>99; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>100; MIPS4-NEXT: # <MCOperand Expr:specifier(4027,a)>>101;102; MIPS64R6-LABEL: f1:103; MIPS64R6: # %bb.0:104; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #[[#MCINST9:]] LUi64105; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5:]]>106; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,a)>>107; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #[[#MCINST10:]] DADDiu108; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>109; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>110; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,a)>>111; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11:]] DSLL112; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>113; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>114; MIPS64R6-NEXT: # <MCOperand Imm:16>>115; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #[[#MCINST10]] DADDiu116; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>117; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>118; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,a)>>119; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL120; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>121; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>122; MIPS64R6-NEXT: # <MCOperand Imm:16>>123; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13:]] JALR64124; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8:]]>125; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6:]]>>126; MIPS64R6-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST12:]] SB64127; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7:]]>128; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>129; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,a)>>130;131; MMR5FP64-LABEL: f1:132; MMR5FP64: # %bb.0:133; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST4:]] LUi_MM134; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1:]]>135; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,a)>>136; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5:]] JR_MM137; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>138; MMR5FP64-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST6:]] SB_MM139; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3:]]>140; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>141; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,a)>>142;143; MIPS32R5FP643-LABEL: f1:144; MIPS32R5FP643: # %bb.0:145; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #[[#MCINST1:]] LUi146; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1:]]>147; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,a)>>148; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2:]] JR149; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2:]]>>150; MIPS32R5FP643-NEXT: sb $4, %lo(a)($1) # <MCInst #[[#MCINST3:]] SB151; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3:]]>152; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>153; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,a)>>154 store i8 %a, ptr @a155 ret void156}157 158define void @f2(i16 %a) {159; MIPS32-LABEL: f2:160; MIPS32: # %bb.0:161; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi162; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>163; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,b)>>164; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR165; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>166; MIPS32-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH167; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>168; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>169; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,b)>>170;171; MMR3-LABEL: f2:172; MMR3: # %bb.0:173; MMR3-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM174; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>175; MMR3-NEXT: # <MCOperand Expr:specifier(4024,b)>>176; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM177; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>178; MMR3-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM179; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>180; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>181; MMR3-NEXT: # <MCOperand Expr:specifier(4027,b)>>182;183; MIPS32R6-LABEL: f2:184; MIPS32R6: # %bb.0:185; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi186; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>187; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,b)>>188; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR189; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>190; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>191; MIPS32R6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH192; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>193; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>194; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,b)>>195;196; MMR6-LABEL: f2:197; MMR6: # %bb.0:198; MMR6-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM199; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>200; MMR6-NEXT: # <MCOperand Expr:specifier(4024,b)>>201; MMR6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM202; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>203; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>204; MMR6-NEXT: # <MCOperand Expr:specifier(4027,b)>>205; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM206; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>207;208; MIPS4-LABEL: f2:209; MIPS4: # %bb.0:210; MIPS4-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64211; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>212; MIPS4-NEXT: # <MCOperand Expr:specifier(4026,b)>>213; MIPS4-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu214; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>215; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>216; MIPS4-NEXT: # <MCOperand Expr:specifier(4025,b)>>217; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL218; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>219; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>220; MIPS4-NEXT: # <MCOperand Imm:16>>221; MIPS4-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu222; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>223; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>224; MIPS4-NEXT: # <MCOperand Expr:specifier(4024,b)>>225; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL226; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>227; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>228; MIPS4-NEXT: # <MCOperand Imm:16>>229; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR230; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>231; MIPS4-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST16:]] SH64232; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG7]]>233; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>234; MIPS4-NEXT: # <MCOperand Expr:specifier(4027,b)>>235;236; MIPS64R6-LABEL: f2:237; MIPS64R6: # %bb.0:238; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #[[#MCINST9]] LUi64239; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>240; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,b)>>241; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #[[#MCINST10]] DADDiu242; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>243; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>244; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,b)>>245; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL246; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>247; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>248; MIPS64R6-NEXT: # <MCOperand Imm:16>>249; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #[[#MCINST10]] DADDiu250; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>251; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>252; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,b)>>253; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL254; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>255; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>256; MIPS64R6-NEXT: # <MCOperand Imm:16>>257; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64258; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>259; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>260; MIPS64R6-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST16:]] SH64261; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>262; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>263; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,b)>>264;265; MMR5FP64-LABEL: f2:266; MMR5FP64: # %bb.0:267; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST4]] LUi_MM268; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>269; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,b)>>270; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM271; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>272; MMR5FP64-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST15:]] SH_MM273; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>274; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>275; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,b)>>276;277; MIPS32R5FP643-LABEL: f2:278; MIPS32R5FP643: # %bb.0:279; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #[[#MCINST1]] LUi280; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>281; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,b)>>282; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR283; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>284; MIPS32R5FP643-NEXT: sh $4, %lo(b)($1) # <MCInst #[[#MCINST14:]] SH285; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>286; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>287; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,b)>>288 store i16 %a, ptr @b289 ret void290}291 292define void @f3(i32 %a) {293; MIPS32-LABEL: f3:294; MIPS32: # %bb.0:295; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi296; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>297; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,c)>>298; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR299; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>300; MIPS32-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW301; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>302; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>303; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,c)>>304;305; MMR3-LABEL: f3:306; MMR3: # %bb.0:307; MMR3-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM308; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>309; MMR3-NEXT: # <MCOperand Expr:specifier(4024,c)>>310; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM311; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>312; MMR3-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM313; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>314; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>315; MMR3-NEXT: # <MCOperand Expr:specifier(4027,c)>>316;317; MIPS32R6-LABEL: f3:318; MIPS32R6: # %bb.0:319; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi320; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>321; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,c)>>322; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR323; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>324; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>325; MIPS32R6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW326; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>327; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>328; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,c)>>329;330; MMR6-LABEL: f3:331; MMR6: # %bb.0:332; MMR6-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM333; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>334; MMR6-NEXT: # <MCOperand Expr:specifier(4024,c)>>335; MMR6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM336; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>337; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>338; MMR6-NEXT: # <MCOperand Expr:specifier(4027,c)>>339; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM340; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>341;342; MIPS4-LABEL: f3:343; MIPS4: # %bb.0:344; MIPS4-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64345; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>346; MIPS4-NEXT: # <MCOperand Expr:specifier(4026,c)>>347; MIPS4-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu348; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>349; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>350; MIPS4-NEXT: # <MCOperand Expr:specifier(4025,c)>>351; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL352; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>353; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>354; MIPS4-NEXT: # <MCOperand Imm:16>>355; MIPS4-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu356; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>357; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>358; MIPS4-NEXT: # <MCOperand Expr:specifier(4024,c)>>359; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL360; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>361; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>362; MIPS4-NEXT: # <MCOperand Imm:16>>363; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR364; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>365; MIPS4-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST19:]] SW64366; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG7]]>367; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>368; MIPS4-NEXT: # <MCOperand Expr:specifier(4027,c)>>369;370; MIPS64R6-LABEL: f3:371; MIPS64R6: # %bb.0:372; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #[[#MCINST9]] LUi64373; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>374; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,c)>>375; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #[[#MCINST10]] DADDiu376; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>377; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>378; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,c)>>379; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL380; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>381; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>382; MIPS64R6-NEXT: # <MCOperand Imm:16>>383; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #[[#MCINST10]] DADDiu384; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>385; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>386; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,c)>>387; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL388; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>389; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>390; MIPS64R6-NEXT: # <MCOperand Imm:16>>391; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64392; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>393; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>394; MIPS64R6-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST19:]] SW64395; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>396; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>397; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,c)>>398;399; MMR5FP64-LABEL: f3:400; MMR5FP64: # %bb.0:401; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST4]] LUi_MM402; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>403; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,c)>>404; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM405; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>406; MMR5FP64-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST18:]] SW_MM407; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>408; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>409; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,c)>>410;411; MIPS32R5FP643-LABEL: f3:412; MIPS32R5FP643: # %bb.0:413; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #[[#MCINST1]] LUi414; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>415; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,c)>>416; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR417; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>418; MIPS32R5FP643-NEXT: sw $4, %lo(c)($1) # <MCInst #[[#MCINST17:]] SW419; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>420; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>421; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,c)>>422 store i32 %a, ptr @c423 ret void424}425 426define void @f4(i64 %a) {427; MIPS32-LABEL: f4:428; MIPS32: # %bb.0:429; MIPS32-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi430; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>431; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,d)>>432; MIPS32-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW433; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG3]]>434; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>435; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,d)>>436; MIPS32-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu437; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>438; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>439; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,d)>>440; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR441; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>442; MIPS32-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW443; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG9:]]>444; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>445; MIPS32-NEXT: # <MCOperand Imm:4>>446;447; MMR3-LABEL: f4:448; MMR3: # %bb.0:449; MMR3-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM450; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>451; MMR3-NEXT: # <MCOperand Expr:specifier(4024,d)>>452; MMR3-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM453; MMR3-NEXT: # <MCOperand Reg:[[#MCREG3]]>454; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>455; MMR3-NEXT: # <MCOperand Expr:specifier(4027,d)>>456; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM457; MMR3-NEXT: # <MCOperand Reg:[[#MCREG10:]]>458; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>459; MMR3-NEXT: # <MCOperand Expr:specifier(4027,d)>>460; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM461; MMR3-NEXT: # <MCOperand Reg:[[#MCREG9:]]>462; MMR3-NEXT: # <MCOperand Reg:[[#MCREG10]]>463; MMR3-NEXT: # <MCOperand Imm:4>>464; MMR3-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM465; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>466;467; MIPS32R6-LABEL: f4:468; MIPS32R6: # %bb.0:469; MIPS32R6-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi470; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>471; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,d)>>472; MIPS32R6-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW473; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG3]]>474; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>475; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,d)>>476; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu477; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>478; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>479; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,d)>>480; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR481; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>482; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>483; MIPS32R6-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW484; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG9:]]>485; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>486; MIPS32R6-NEXT: # <MCOperand Imm:4>>487;488; MMR6-LABEL: f4:489; MMR6: # %bb.0:490; MMR6-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM491; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>492; MMR6-NEXT: # <MCOperand Expr:specifier(4024,d)>>493; MMR6-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM494; MMR6-NEXT: # <MCOperand Reg:[[#MCREG3]]>495; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>496; MMR6-NEXT: # <MCOperand Expr:specifier(4027,d)>>497; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM498; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10:]]>499; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>500; MMR6-NEXT: # <MCOperand Expr:specifier(4027,d)>>501; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM502; MMR6-NEXT: # <MCOperand Reg:[[#MCREG9:]]>503; MMR6-NEXT: # <MCOperand Reg:[[#MCREG10]]>504; MMR6-NEXT: # <MCOperand Imm:4>>505; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM506; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>507;508; MIPS4-LABEL: f4:509; MIPS4: # %bb.0:510; MIPS4-NEXT: lui $1, %highest(d) # <MCInst #[[#MCINST9]] LUi64511; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>512; MIPS4-NEXT: # <MCOperand Expr:specifier(4026,d)>>513; MIPS4-NEXT: daddiu $1, $1, %higher(d) # <MCInst #[[#MCINST10]] DADDiu514; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>515; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>516; MIPS4-NEXT: # <MCOperand Expr:specifier(4025,d)>>517; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL518; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>519; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>520; MIPS4-NEXT: # <MCOperand Imm:16>>521; MIPS4-NEXT: daddiu $1, $1, %hi(d) # <MCInst #[[#MCINST10]] DADDiu522; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>523; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>524; MIPS4-NEXT: # <MCOperand Expr:specifier(4024,d)>>525; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL526; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>527; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>528; MIPS4-NEXT: # <MCOperand Imm:16>>529; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR530; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>531; MIPS4-NEXT: sd $4, %lo(d)($1) # <MCInst #[[#MCINST23:]] SD532; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG7]]>533; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>534; MIPS4-NEXT: # <MCOperand Expr:specifier(4027,d)>>535;536; MIPS64R6-LABEL: f4:537; MIPS64R6: # %bb.0:538; MIPS64R6-NEXT: lui $1, %highest(d) # <MCInst #[[#MCINST9]] LUi64539; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>540; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,d)>>541; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # <MCInst #[[#MCINST10]] DADDiu542; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>543; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>544; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,d)>>545; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL546; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>547; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>548; MIPS64R6-NEXT: # <MCOperand Imm:16>>549; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # <MCInst #[[#MCINST10]] DADDiu550; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>551; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>552; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,d)>>553; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL554; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>555; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>556; MIPS64R6-NEXT: # <MCOperand Imm:16>>557; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64558; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>559; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>560; MIPS64R6-NEXT: sd $4, %lo(d)($1) # <MCInst #[[#MCINST23:]] SD561; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG7]]>562; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>563; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,d)>>564;565; MMR5FP64-LABEL: f4:566; MMR5FP64: # %bb.0:567; MMR5FP64-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST4]] LUi_MM568; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>569; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,d)>>570; MMR5FP64-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST18]] SW_MM571; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG3]]>572; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>573; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,d)>>574; MMR5FP64-NEXT: addiu $2, $1, %lo(d) # <MCInst #[[#MCINST21:]] ADDiu_MM575; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG10:]]>576; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>577; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,d)>>578; MMR5FP64-NEXT: sw16 $5, 4($2) # <MCInst #[[#MCINST22:]] SW16_MM579; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG9:]]>580; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG10]]>581; MMR5FP64-NEXT: # <MCOperand Imm:4>>582; MMR5FP64-NEXT: jrc $ra # <MCInst #[[#MCINST8:]] JRC16_MM583; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>584;585; MIPS32R5FP643-LABEL: f4:586; MIPS32R5FP643: # %bb.0:587; MIPS32R5FP643-NEXT: lui $1, %hi(d) # <MCInst #[[#MCINST1]] LUi588; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>589; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,d)>>590; MIPS32R5FP643-NEXT: sw $4, %lo(d)($1) # <MCInst #[[#MCINST17]] SW591; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG3]]>592; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>593; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,d)>>594; MIPS32R5FP643-NEXT: addiu $1, $1, %lo(d) # <MCInst #[[#MCINST20:]] ADDiu595; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>596; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>597; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,d)>>598; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR599; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>600; MIPS32R5FP643-NEXT: sw $5, 4($1) # <MCInst #[[#MCINST17]] SW601; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG9:]]>602; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>603; MIPS32R5FP643-NEXT: # <MCOperand Imm:4>>604 store i64 %a, ptr @d605 ret void606}607 608define void @f5(float %e) {609; MIPS32-LABEL: f5:610; MIPS32: # %bb.0:611; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi612; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>613; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,e)>>614; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR615; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>616; MIPS32-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1617; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG11:]]>618; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>619; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,e)>>620;621; MMR3-LABEL: f5:622; MMR3: # %bb.0:623; MMR3-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM624; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>625; MMR3-NEXT: # <MCOperand Expr:specifier(4024,e)>>626; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM627; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>628; MMR3-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM629; MMR3-NEXT: # <MCOperand Reg:[[#MCREG11:]]>630; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>631; MMR3-NEXT: # <MCOperand Expr:specifier(4027,e)>>632;633; MIPS32R6-LABEL: f5:634; MIPS32R6: # %bb.0:635; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi636; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>637; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,e)>>638; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR639; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>640; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>641; MIPS32R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1642; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG11:]]>643; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>644; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,e)>>645;646; MMR6-LABEL: f5:647; MMR6: # %bb.0:648; MMR6-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM649; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>650; MMR6-NEXT: # <MCOperand Expr:specifier(4024,e)>>651; MMR6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM652; MMR6-NEXT: # <MCOperand Reg:[[#MCREG11:]]>653; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>654; MMR6-NEXT: # <MCOperand Expr:specifier(4027,e)>>655; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM656; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>657;658; MIPS4-LABEL: f5:659; MIPS4: # %bb.0:660; MIPS4-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64661; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>662; MIPS4-NEXT: # <MCOperand Expr:specifier(4026,e)>>663; MIPS4-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu664; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>665; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>666; MIPS4-NEXT: # <MCOperand Expr:specifier(4025,e)>>667; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL668; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>669; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>670; MIPS4-NEXT: # <MCOperand Imm:16>>671; MIPS4-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu672; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>673; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>674; MIPS4-NEXT: # <MCOperand Expr:specifier(4024,e)>>675; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL676; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>677; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>678; MIPS4-NEXT: # <MCOperand Imm:16>>679; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR680; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>681; MIPS4-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1682; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG11:]]>683; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>684; MIPS4-NEXT: # <MCOperand Expr:specifier(4027,e)>>685;686; MIPS64R6-LABEL: f5:687; MIPS64R6: # %bb.0:688; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #[[#MCINST9]] LUi64689; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>690; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,e)>>691; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #[[#MCINST10]] DADDiu692; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>693; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>694; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,e)>>695; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL696; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>697; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>698; MIPS64R6-NEXT: # <MCOperand Imm:16>>699; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #[[#MCINST10]] DADDiu700; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>701; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>702; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,e)>>703; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL704; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>705; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>706; MIPS64R6-NEXT: # <MCOperand Imm:16>>707; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64708; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>709; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>710; MIPS64R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1711; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG11:]]>712; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>713; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,e)>>714;715; MMR5FP64-LABEL: f5:716; MMR5FP64: # %bb.0:717; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST4]] LUi_MM718; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>719; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,e)>>720; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM721; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>722; MMR5FP64-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST25:]] SWC1_MM723; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG11:]]>724; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>725; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,e)>>726;727; MIPS32R5FP643-LABEL: f5:728; MIPS32R5FP643: # %bb.0:729; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #[[#MCINST1]] LUi730; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>731; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,e)>>732; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR733; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>734; MIPS32R5FP643-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #[[#MCINST24:]] SWC1735; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG11:]]>736; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>737; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,e)>>738 store float %e, ptr @e739 ret void740}741 742define void @f6(double %f) {743; MIPS32-LABEL: f6:744; MIPS32: # %bb.0:745; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi746; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>747; MIPS32-NEXT: # <MCOperand Expr:specifier(4024,f)>>748; MIPS32-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR749; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG2]]>>750; MIPS32-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST26:]] SDC1751; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG12:]]>752; MIPS32-NEXT: # <MCOperand Reg:[[#MCREG1]]>753; MIPS32-NEXT: # <MCOperand Expr:specifier(4027,f)>>754;755; MMR3-LABEL: f6:756; MMR3: # %bb.0:757; MMR3-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM758; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>759; MMR3-NEXT: # <MCOperand Expr:specifier(4024,f)>>760; MMR3-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM761; MMR3-NEXT: # <MCOperand Reg:[[#MCREG2]]>>762; MMR3-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST27:]] SDC1_MM_D32763; MMR3-NEXT: # <MCOperand Reg:[[#MCREG12:]]>764; MMR3-NEXT: # <MCOperand Reg:[[#MCREG1]]>765; MMR3-NEXT: # <MCOperand Expr:specifier(4027,f)>>766;767; MIPS32R6-LABEL: f6:768; MIPS32R6: # %bb.0:769; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi770; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>771; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4024,f)>>772; MIPS32R6-NEXT: jr $ra # <MCInst #[[#MCINST7]] JALR773; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG4]]>774; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>775; MIPS32R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164776; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG13:]]>777; MIPS32R6-NEXT: # <MCOperand Reg:[[#MCREG1]]>778; MIPS32R6-NEXT: # <MCOperand Expr:specifier(4027,f)>>779;780; MMR6-LABEL: f6:781; MMR6: # %bb.0:782; MMR6-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM783; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>784; MMR6-NEXT: # <MCOperand Expr:specifier(4024,f)>>785; MMR6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST29:]] SDC1_D64_MMR6786; MMR6-NEXT: # <MCOperand Reg:[[#MCREG13:]]>787; MMR6-NEXT: # <MCOperand Reg:[[#MCREG1]]>788; MMR6-NEXT: # <MCOperand Expr:specifier(4027,f)>>789; MMR6-NEXT: jrc $ra # <MCInst #[[#MCINST8]] JRC16_MM790; MMR6-NEXT: # <MCOperand Reg:[[#MCREG2]]>>791;792; MIPS4-LABEL: f6:793; MIPS4: # %bb.0:794; MIPS4-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64795; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>796; MIPS4-NEXT: # <MCOperand Expr:specifier(4026,f)>>797; MIPS4-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu798; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>799; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>800; MIPS4-NEXT: # <MCOperand Expr:specifier(4025,f)>>801; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL802; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>803; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>804; MIPS4-NEXT: # <MCOperand Imm:16>>805; MIPS4-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu806; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>807; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>808; MIPS4-NEXT: # <MCOperand Expr:specifier(4024,f)>>809; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL810; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>811; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>812; MIPS4-NEXT: # <MCOperand Imm:16>>813; MIPS4-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR814; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG6]]>>815; MIPS4-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164816; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG13:]]>817; MIPS4-NEXT: # <MCOperand Reg:[[#MCREG5]]>818; MIPS4-NEXT: # <MCOperand Expr:specifier(4027,f)>>819;820; MIPS64R6-LABEL: f6:821; MIPS64R6: # %bb.0:822; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #[[#MCINST9]] LUi64823; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>824; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4026,f)>>825; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #[[#MCINST10]] DADDiu826; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>827; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>828; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4025,f)>>829; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL830; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>831; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>832; MIPS64R6-NEXT: # <MCOperand Imm:16>>833; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #[[#MCINST10]] DADDiu834; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>835; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>836; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4024,f)>>837; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #[[#MCINST11]] DSLL838; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>839; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>840; MIPS64R6-NEXT: # <MCOperand Imm:16>>841; MIPS64R6-NEXT: jr $ra # <MCInst #[[#MCINST13]] JALR64842; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG8]]>843; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG6]]>>844; MIPS64R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164845; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG13:]]>846; MIPS64R6-NEXT: # <MCOperand Reg:[[#MCREG5]]>847; MIPS64R6-NEXT: # <MCOperand Expr:specifier(4027,f)>>848;849; MMR5FP64-LABEL: f6:850; MMR5FP64: # %bb.0:851; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST4]] LUi_MM852; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>853; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4024,f)>>854; MMR5FP64-NEXT: jr $ra # <MCInst #[[#MCINST5]] JR_MM855; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG2]]>>856; MMR5FP64-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST30:]] SDC1_MM_D64857; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG13:]]>858; MMR5FP64-NEXT: # <MCOperand Reg:[[#MCREG1]]>859; MMR5FP64-NEXT: # <MCOperand Expr:specifier(4027,f)>>860;861; MIPS32R5FP643-LABEL: f6:862; MIPS32R5FP643: # %bb.0:863; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #[[#MCINST1]] LUi864; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>865; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4024,f)>>866; MIPS32R5FP643-NEXT: jr $ra # <MCInst #[[#MCINST2]] JR867; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG2]]>>868; MIPS32R5FP643-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #[[#MCINST28:]] SDC164869; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG13:]]>870; MIPS32R5FP643-NEXT: # <MCOperand Reg:[[#MCREG1]]>871; MIPS32R5FP643-NEXT: # <MCOperand Expr:specifier(4027,f)>>872 store double %f, ptr @f873 ret void874}875