212 lines · plain
1; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s \2; RUN: -check-prefixes=NOT-R2-R6,GP32,NOT-MM,PRE43; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s \4; RUN: -check-prefixes=NOT-R2-R6,GP32,NOT-MM5; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \6; RUN: -check-prefixes=R2-R6,GP32,NOT-MM7; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \8; RUN: -check-prefixes=R2-R6,GP32,NOT-MM9; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \10; RUN: -check-prefixes=R2-R6,GP32,NOT-MM11; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \12; RUN: -check-prefixes=R2-R6,GP32,NOT-MM13; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \14; RUN: -check-prefixes=MM32,MMR315; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \16; RUN: -check-prefixes=MM32,MMR617; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \18; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R219; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \20; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R221; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \22; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R223; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \24; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R225; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \26; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R227; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \28; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R229; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \30; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R231 32define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {33entry:34; ALL-LABEL: sub_i1:35 36 ; NOT-MM: xor $[[T0:[0-9]+]], $4, $537 38 ; MM: xor16 $[[T0:[0-9]+]], $4, $539 40 %r = sub i1 %a, %b41 ret i1 %r42}43 44define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {45entry:46; ALL-LABEL: sub_i8:47 48 ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $549 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 2450 ; NOT-R2-R6: sra $2, $[[T0]], 2451 52 ; R2-R6: subu $[[T0:[0-9]+]], $4, $553 ; R2-R6: seb $2, $[[T0:[0-9]+]]54 55 ; MM: subu16 $[[T0:[0-9]+]], $4, $556 ; MM: seb $[[T0]], $[[T0]]57 58 %r = sub i8 %a, %b59 ret i8 %r60}61 62define signext i16 @sub_i16(i16 signext %a, i16 signext %b) {63entry:64; ALL-LABEL: sub_i16:65 66 ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $567 ; NOT-R2-R6: sll $[[T0]], $[[T0]], 1668 ; NOT-R2-R6: sra $2, $[[T0]], 1669 70 ; R2-R6: subu $[[T0:[0-9]+]], $4, $571 ; R2-R6: seh $2, $[[T0:[0-9]+]]72 73 ; MM: subu16 $[[T0:[0-9]+]], $4, $574 ; MM: seh $[[T0]], $[[T0]]75 76 %r = sub i16 %a, %b77 ret i16 %r78}79 80define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {81entry:82; ALL-LABEL: sub_i32:83 84 ; NOT-MM: subu $2, $4, $585 86 ; MM: subu16 $2, $4, $587 88 %r = sub i32 %a, %b89 ret i32 %r90}91 92define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {93entry:94; ALL-LABEL: sub_i64:95 96 ; GP32: sltu $[[T0:[0-9]+]], $5, $797 ; GP32: subu $2, $4, $698 ; GP32: subu $2, $2, $[[T0]]99 ; GP32: subu $3, $5, $7100 101 ; MM32: sltu $[[T0:[0-9]+]], $5, $7102 ; MM32: subu16 $3, $4, $6103 ; MM32: subu16 $2, $3, $[[T0]]104 ; MM32: subu16 $3, $5, $7105 106 ; GP64: dsubu $2, $4, $5107 108 %r = sub i64 %a, %b109 ret i64 %r110}111 112define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {113entry:114; ALL-LABEL: sub_i128:115 116; PRE4: lw $[[T0:[0-9]+]], 24($sp)117; PRE4: lw $[[T1:[0-9]+]], 28($sp)118; PRE4: sltu $[[T2:[0-9]+]], $7, $[[T1]]119; PRE4: xor $[[T3:[0-9]+]], $6, $[[T0]]120; PRE4: sltiu $[[T4:[0-9]+]], $[[T3]], 1121; PRE4: bnez $[[T4]]122; PRE4: move $[[T5:[0-9]+]], $[[T2]]123; PRE4: sltu $[[T5]], $6, $[[T0]]124 125; PRE4: lw $[[T6:[0-9]+]], 20($sp)126; PRE4: subu $[[T7:[0-9]+]], $5, $[[T6]]127; PRE4: subu $[[T8:[0-9]+]], $[[T7]], $[[T5]]128; PRE4: sltu $[[T9:[0-9]+]], $[[T7]], $[[T5]]129; PRE4: sltu $[[T10:[0-9]+]], $5, $[[T6]]130; PRE4: lw $[[T11:[0-9]+]], 16($sp)131; PRE4: subu $[[T12:[0-9]+]], $4, $[[T11]]132; PRE4: subu $[[T13:[0-9]+]], $[[T12]], $[[T10]]133; PRE4: subu $[[T14:[0-9]+]], $[[T13]], $[[T9]]134; PRE4: subu $[[T15:[0-9]+]], $6, $[[T0]]135; PRE4: subu $[[T16:[0-9]+]], $[[T15]], $[[T2]]136; PRE4: subu $5, $7, $[[T1]]137 138; MMR3: lw $[[T1:[0-9]+]], 48($sp)139; MMR3: sltu $[[T2:[0-9]+]], $6, $[[T1]]140; MMR3: xor $[[T3:[0-9]+]], $6, $[[T1]]141; MMR3: lw $[[T4:[0-9]+]], 52($sp)142; MMR3: sltu $[[T5:[0-9]+]], $7, $[[T4]]143; MMR3: movz $[[T6:[0-9]+]], $[[T5]], $[[T3]]144; MMR3: lw $[[T7:[0-8]+]], 44($sp)145; MMR3: subu16 $[[T8:[0-9]+]], $5, $[[T7]]146; MMR3: subu16 $[[T9:[0-9]+]], $[[T8]], $[[T6]]147; MMR3: sltu $[[T10:[0-9]+]], $[[T8]], $[[T2]]148; MMR3: sltu $[[T11:[0-9]+]], $5, $[[T7]]149; MMR3: lw $[[T12:[0-9]+]], 40($sp)150; MMR3: lw $[[T13:[0-9]+]], 12($sp)151; MMR3: subu16 $[[T14:[0-9]+]], $[[T13]], $[[T12]]152; MMR3: subu16 $[[T15:[0-9]+]], $[[T14]], $[[T11]]153; MMR3: subu16 $[[T16:[0-9]+]], $[[T15]], $[[T10]]154; MMR3: subu16 $[[T17:[0-9]+]], $6, $[[T1]]155; MMR3: subu16 $[[T18:[0-9]+]], $[[T17]], $7156; MMR3: lw $[[T19:[0-9]+]], 8($sp)157; MMR3: lw $[[T20:[0-9]+]], 0($sp)158; MMR3: subu16 $5, $[[T19]], $[[T20]]159 160; MMR6: move $[[T0:[0-9]+]], $7161; MMR6: sw $7, 8($sp)162; MMR6: move $[[T1:[0-9]+]], $5163; MMR6: sw $4, 12($sp)164; MMR6: lw $[[T2:[0-9]+]], 48($sp)165; MMR6: sltu $[[T3:[0-9]+]], $6, $[[T2]]166; MMR6: xor $[[T4:[0-9]+]], $6, $[[T2]]167; MMR6: sltiu $[[T5:[0-9]+]], $[[T4]], 1168; MMR6: seleqz $[[T6:[0-9]+]], $[[T3]], $[[T5]]169; MMR6: lw $[[T7:[0-9]+]], 52($sp)170; MMR6: sltu $[[T8:[0-9]+]], $[[T0]], $[[T7]]171; MMR6: selnez $[[T9:[0-9]+]], $[[T8]], $[[T5]]172; MMR6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]]173; MMR6: lw $[[T11:[0-9]+]], 44($sp)174; MMR6: subu16 $[[T12:[0-9]+]], $[[T1]], $[[T11]]175; MMR6: subu16 $[[T13:[0-9]+]], $[[T12]], $[[T7]]176; MMR6: sltu $[[T16:[0-9]+]], $[[T12]], $[[T7]]177; MMR6: sltu $[[T17:[0-9]+]], $[[T1]], $[[T11]]178; MMR6: lw $[[T18:[0-9]+]], 40($sp)179; MMR6: lw $[[T19:[0-9]+]], 12($sp)180; MMR6: subu16 $[[T20:[0-9]+]], $[[T19]], $[[T18]]181; MMR6: subu16 $[[T21:[0-9]+]], $[[T20]], $[[T17]]182; MMR6: subu16 $[[T22:[0-9]+]], $[[T21]], $[[T16]]183; MMR6: subu16 $[[T23:[0-9]+]], $6, $[[T2]]184; MMR6: subu16 $4, $[[T23]], $5185; MMR6: lw $[[T24:[0-9]+]], 8($sp)186; MMR6: lw $[[T25:[0-9]+]], 0($sp)187; MMR6: subu16 $5, $[[T24]], $[[T25]]188; MMR6: lw $3, 4($sp)189 190; FIXME: The sltu, dsll, dsrl pattern here occurs when an i32 is zero191; extended to 64 bits. Fortunately slt(i)(u) actually gives an i1.192; These should be combined away.193 194; GP64-NOT-R2: dsubu $1, $4, $6195; GP64-NOT-R2: sltu $[[T0:[0-9]+]], $5, $7196; GP64-NOT-R2: dsll $[[T1:[0-9]+]], $[[T0]], 32197; GP64-NOT-R2: dsrl $[[T2:[0-9]+]], $[[T1]], 32198; GP64-NOT-R2: dsubu $2, $1, $[[T2]]199; GP64-NOT-R2: dsubu $3, $5, $7200 201; FIXME: Likewise for the sltu, dext here.202 203; GP64-R2: dsubu $1, $4, $6204; GP64-R2: sltu $[[T0:[0-9]+]], $5, $7205; GP64-R2: dext $[[T1:[0-9]+]], $[[T0]], 0, 32206; GP64-R2: dsubu $2, $1, $[[T1]]207; GP64-R2: dsubu $3, $5, $7208 209 %r = sub i128 %a, %b210 ret i128 %r211}212