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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \3; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS24; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \5; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS326 7; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \8; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS39; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \10; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS6411 12; RUN: llc < %s -mtriple=mips -mcpu=mips2 -O0 -relocation-model=pic \13; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS2-O014; RUN: llc < %s -mtriple=mips -mcpu=mips32 -O0 -relocation-model=pic \15; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS32-O016 17define signext i32 @srem_i32(i32 signext %a, i32 signext %b, i32 signext %c) {18; MIPS2-LABEL: srem_i32:19; MIPS2: # %bb.0: # %entry20; MIPS2-NEXT: div $zero, $4, $521; MIPS2-NEXT: teq $5, $zero, 722; MIPS2-NEXT: mfhi $123; MIPS2-NEXT: nop24; MIPS2-NEXT: nop25; MIPS2-NEXT: div $zero, $1, $626; MIPS2-NEXT: teq $6, $zero, 727; MIPS2-NEXT: mfhi $228; MIPS2-NEXT: jr $ra29; MIPS2-NEXT: nop30;31; MIPS32-LABEL: srem_i32:32; MIPS32: # %bb.0: # %entry33; MIPS32-NEXT: div $zero, $4, $534; MIPS32-NEXT: teq $5, $zero, 735; MIPS32-NEXT: mfhi $136; MIPS32-NEXT: div $zero, $1, $637; MIPS32-NEXT: teq $6, $zero, 738; MIPS32-NEXT: jr $ra39; MIPS32-NEXT: mfhi $240;41entry:42 %rem = srem i32 %a, %b43 %rem1 = srem i32 %rem, %c44 ret i32 %rem145}46 47define signext i64 @srem_i64(i64 signext %a, i64 signext %b, i64 signext %c) {48; MIPS3-LABEL: srem_i64:49; MIPS3: # %bb.0: # %entry50; MIPS3-NEXT: ddiv $zero, $4, $551; MIPS3-NEXT: teq $5, $zero, 752; MIPS3-NEXT: mfhi $153; MIPS3-NEXT: nop54; MIPS3-NEXT: nop55; MIPS3-NEXT: ddiv $zero, $1, $656; MIPS3-NEXT: teq $6, $zero, 757; MIPS3-NEXT: mfhi $258; MIPS3-NEXT: jr $ra59; MIPS3-NEXT: nop60;61; MIPS64-LABEL: srem_i64:62; MIPS64: # %bb.0: # %entry63; MIPS64-NEXT: ddiv $zero, $4, $564; MIPS64-NEXT: teq $5, $zero, 765; MIPS64-NEXT: mfhi $166; MIPS64-NEXT: ddiv $zero, $1, $667; MIPS64-NEXT: teq $6, $zero, 768; MIPS64-NEXT: jr $ra69; MIPS64-NEXT: mfhi $270;71entry:72 %rem = srem i64 %a, %b73 %rem1 = srem i64 %rem, %c74 ret i64 %rem175}76 77define signext i32 @srem_lw_srem_i32(i32 signext %a, i32 signext %b, i32 signext %c) {78; MIPS2-O0-LABEL: srem_lw_srem_i32:79; MIPS2-O0: # %bb.0: # %entry80; MIPS2-O0-NEXT: addiu $sp, $sp, -1681; MIPS2-O0-NEXT: .cfi_def_cfa_offset 1682; MIPS2-O0-NEXT: sw $4, 12($sp)83; MIPS2-O0-NEXT: sw $5, 8($sp) 84; MIPS2-O0-NEXT: sw $6, 4($sp)85; MIPS2-O0-NEXT: lw $2, 12($sp)86; MIPS2-O0-NEXT: lw $1, 8($sp)87; MIPS2-O0-NEXT: div $zero, $2, $188; MIPS2-O0-NEXT: teq $1, $zero, 789; MIPS2-O0-NEXT: mfhi $290; MIPS2-O0-NEXT: lw $1, 4($sp)91; MIPS2-O0-NEXT: nop92; MIPS2-O0-NEXT: div $zero, $2, $193; MIPS2-O0-NEXT: teq $1, $zero, 794; MIPS2-O0-NEXT: mfhi $295; MIPS2-O0-NEXT: addiu $sp, $sp, 1696; MIPS2-O0-NEXT: jr $ra97; MIPS2-O0-NEXT: nop98;99; MIPS32-O0-LABEL: srem_lw_srem_i32:100; MIPS32-O0: # %bb.0: # %entry101; MIPS32-O0-NEXT: addiu $sp, $sp, -16102; MIPS32-O0-NEXT: .cfi_def_cfa_offset 16103; MIPS32-O0-NEXT: sw $4, 12($sp)104; MIPS32-O0-NEXT: sw $5, 8($sp) 105; MIPS32-O0-NEXT: sw $6, 4($sp)106; MIPS32-O0-NEXT: lw $2, 12($sp)107; MIPS32-O0-NEXT: lw $1, 8($sp)108; MIPS32-O0-NEXT: div $zero, $2, $1109; MIPS32-O0-NEXT: teq $1, $zero, 7110; MIPS32-O0-NEXT: mfhi $2111; MIPS32-O0-NEXT: lw $1, 4($sp)112; MIPS32-O0-NEXT: div $zero, $2, $1113; MIPS32-O0-NEXT: teq $1, $zero, 7114; MIPS32-O0-NEXT: mfhi $2115; MIPS32-O0-NEXT: addiu $sp, $sp, 16116; MIPS32-O0-NEXT: jr $ra117; MIPS32-O0-NEXT: nop118;119entry:120 %a.addr = alloca i32, align 4121 %b.addr = alloca i32, align 4122 %c.addr = alloca i32, align 4123 store i32 %a, ptr %a.addr, align 4124 store i32 %b, ptr %b.addr, align 4125 store i32 %c, ptr %c.addr, align 4126 %0 = load i32, ptr %a.addr, align 4127 %1 = load i32, ptr %b.addr, align 4128 %rem = srem i32 %0, %1129 %2 = load i32, ptr %c.addr, align 4130 %rem1 = srem i32 %rem, %2131 ret i32 %rem1132}133 134