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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=323; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=324; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=32R65; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP6; RUN: llc -mtriple=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=647; RUN: llc -mtriple=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=648; RUN: llc -mtriple=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=64R69; RUN: llc -mtriple=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=1610 11define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {12; 32-LABEL: madd1:13; 32: # %bb.0: # %entry14; 32-NEXT: sra $1, $6, 3115; 32-NEXT: mtlo $616; 32-NEXT: mthi $117; 32-NEXT: madd $5, $418; 32-NEXT: mfhi $219; 32-NEXT: jr $ra20; 32-NEXT: mflo $321;22; 32R6-LABEL: madd1:23; 32R6: # %bb.0: # %entry24; 32R6-NEXT: mul $1, $5, $425; 32R6-NEXT: addu $3, $1, $626; 32R6-NEXT: sltu $1, $3, $127; 32R6-NEXT: muh $2, $5, $428; 32R6-NEXT: sra $4, $6, 3129; 32R6-NEXT: addu $2, $2, $430; 32R6-NEXT: jr $ra31; 32R6-NEXT: addu $2, $2, $132;33; DSP-LABEL: madd1:34; DSP: # %bb.0: # %entry35; DSP-NEXT: sra $1, $6, 3136; DSP-NEXT: mtlo $6, $ac037; DSP-NEXT: mthi $1, $ac038; DSP-NEXT: madd $ac0, $5, $439; DSP-NEXT: mfhi $2, $ac040; DSP-NEXT: jr $ra41; DSP-NEXT: mflo $3, $ac042;43; 64-LABEL: madd1:44; 64: # %bb.0: # %entry45; 64-NEXT: sll $4, $4, 046; 64-NEXT: sll $5, $5, 047; 64-NEXT: dmult $5, $448; 64-NEXT: mflo $149; 64-NEXT: sll $6, $6, 050; 64-NEXT: jr $ra51; 64-NEXT: daddu $2, $1, $652;53; 64R6-LABEL: madd1:54; 64R6: # %bb.0: # %entry55; 64R6-NEXT: sll $4, $4, 056; 64R6-NEXT: sll $5, $5, 057; 64R6-NEXT: dmul $1, $5, $458; 64R6-NEXT: sll $6, $6, 059; 64R6-NEXT: jr $ra60; 64R6-NEXT: daddu $2, $1, $661;62; 16-LABEL: madd1:63; 16: # %bb.0: # %entry64; 16-NEXT: mult $5, $465; 16-NEXT: mflo $266; 16-NEXT: mfhi $367; 16-NEXT: sra $4, $6, 3168; 16-NEXT: addu $4, $3, $469; 16-NEXT: addu $3, $2, $670; 16-NEXT: sltu $3, $271; 16-NEXT: move $2, $2472; 16-NEXT: addu $2, $4, $273; 16-NEXT: jrc $ra74entry:75 %conv = sext i32 %a to i6476 %conv2 = sext i32 %b to i6477 %mul = mul nsw i64 %conv2, %conv78 %conv4 = sext i32 %c to i6479 %add = add nsw i64 %mul, %conv480 ret i64 %add81}82 83define i64 @madd2(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c) nounwind readnone {84; 32-LABEL: madd2:85; 32: # %bb.0: # %entry86; 32-NEXT: addiu $1, $zero, 087; 32-NEXT: mtlo $688; 32-NEXT: mthi $189; 32-NEXT: maddu $5, $490; 32-NEXT: mfhi $291; 32-NEXT: jr $ra92; 32-NEXT: mflo $393;94; 32R6-LABEL: madd2:95; 32R6: # %bb.0: # %entry96; 32R6-NEXT: mul $1, $5, $497; 32R6-NEXT: addu $3, $1, $698; 32R6-NEXT: sltu $1, $3, $199; 32R6-NEXT: muhu $2, $5, $4100; 32R6-NEXT: jr $ra101; 32R6-NEXT: addu $2, $2, $1102;103; DSP-LABEL: madd2:104; DSP: # %bb.0: # %entry105; DSP-NEXT: addiu $1, $zero, 0106; DSP-NEXT: mtlo $6, $ac0107; DSP-NEXT: mthi $1, $ac0108; DSP-NEXT: maddu $ac0, $5, $4109; DSP-NEXT: mfhi $2, $ac0110; DSP-NEXT: jr $ra111; DSP-NEXT: mflo $3, $ac0112;113; 64-LABEL: madd2:114; 64: # %bb.0: # %entry115; 64-NEXT: dmult $5, $4116; 64-NEXT: mflo $1117; 64-NEXT: jr $ra118; 64-NEXT: daddu $2, $1, $6119;120; 64R6-LABEL: madd2:121; 64R6: # %bb.0: # %entry122; 64R6-NEXT: dmul $1, $5, $4123; 64R6-NEXT: jr $ra124; 64R6-NEXT: daddu $2, $1, $6125;126; 16-LABEL: madd2:127; 16: # %bb.0: # %entry128; 16-NEXT: multu $5, $4129; 16-NEXT: mflo $2130; 16-NEXT: mfhi $4131; 16-NEXT: addu $3, $2, $6132; 16-NEXT: sltu $3, $2133; 16-NEXT: move $2, $24134; 16-NEXT: addu $2, $4, $2135; 16-NEXT: jrc $ra136entry:137 %conv = zext i32 %a to i64138 %conv2 = zext i32 %b to i64139 %mul = mul nsw i64 %conv2, %conv140 %conv4 = zext i32 %c to i64141 %add = add nsw i64 %mul, %conv4142 ret i64 %add143}144 145define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {146; 32-LABEL: madd3:147; 32: # %bb.0: # %entry148; 32-NEXT: mtlo $7149; 32-NEXT: mthi $6150; 32-NEXT: madd $5, $4151; 32-NEXT: mfhi $2152; 32-NEXT: jr $ra153; 32-NEXT: mflo $3154;155; 32R6-LABEL: madd3:156; 32R6: # %bb.0: # %entry157; 32R6-NEXT: mul $1, $5, $4158; 32R6-NEXT: addu $3, $1, $7159; 32R6-NEXT: sltu $1, $3, $1160; 32R6-NEXT: muh $2, $5, $4161; 32R6-NEXT: addu $2, $2, $6162; 32R6-NEXT: jr $ra163; 32R6-NEXT: addu $2, $2, $1164;165; DSP-LABEL: madd3:166; DSP: # %bb.0: # %entry167; DSP-NEXT: mtlo $7, $ac0168; DSP-NEXT: mthi $6, $ac0169; DSP-NEXT: madd $ac0, $5, $4170; DSP-NEXT: mfhi $2, $ac0171; DSP-NEXT: jr $ra172; DSP-NEXT: mflo $3, $ac0173;174; 64-LABEL: madd3:175; 64: # %bb.0: # %entry176; 64-NEXT: sll $4, $4, 0177; 64-NEXT: sll $5, $5, 0178; 64-NEXT: dmult $5, $4179; 64-NEXT: mflo $1180; 64-NEXT: jr $ra181; 64-NEXT: daddu $2, $1, $6182;183; 64R6-LABEL: madd3:184; 64R6: # %bb.0: # %entry185; 64R6-NEXT: sll $4, $4, 0186; 64R6-NEXT: sll $5, $5, 0187; 64R6-NEXT: dmul $1, $5, $4188; 64R6-NEXT: jr $ra189; 64R6-NEXT: daddu $2, $1, $6190;191; 16-LABEL: madd3:192; 16: # %bb.0: # %entry193; 16-NEXT: mult $5, $4194; 16-NEXT: mflo $2195; 16-NEXT: mfhi $3196; 16-NEXT: addu $4, $3, $6197; 16-NEXT: addu $3, $2, $7198; 16-NEXT: sltu $3, $2199; 16-NEXT: move $2, $24200; 16-NEXT: addu $2, $4, $2201; 16-NEXT: jrc $ra202entry:203 %conv = sext i32 %a to i64204 %conv2 = sext i32 %b to i64205 %mul = mul nsw i64 %conv2, %conv206 %add = add nsw i64 %mul, %c207 ret i64 %add208}209 210define i32 @madd4(i32 %a, i32 %b, i32 %c) {211; 32-LABEL: madd4:212; 32: # %bb.0: # %entry213; 32-NEXT: mul $1, $4, $5214; 32-NEXT: jr $ra215; 32-NEXT: addu $2, $6, $1216;217; 32R6-LABEL: madd4:218; 32R6: # %bb.0: # %entry219; 32R6-NEXT: mul $1, $4, $5220; 32R6-NEXT: jr $ra221; 32R6-NEXT: addu $2, $6, $1222;223; DSP-LABEL: madd4:224; DSP: # %bb.0: # %entry225; DSP-NEXT: mul $1, $4, $5226; DSP-NEXT: jr $ra227; DSP-NEXT: addu $2, $6, $1228;229; 64-LABEL: madd4:230; 64: # %bb.0: # %entry231; 64-NEXT: sll $1, $5, 0232; 64-NEXT: sll $2, $4, 0233; 64-NEXT: mul $1, $2, $1234; 64-NEXT: sll $2, $6, 0235; 64-NEXT: jr $ra236; 64-NEXT: addu $2, $2, $1237;238; 64R6-LABEL: madd4:239; 64R6: # %bb.0: # %entry240; 64R6-NEXT: sll $1, $5, 0241; 64R6-NEXT: sll $2, $4, 0242; 64R6-NEXT: mul $1, $2, $1243; 64R6-NEXT: sll $2, $6, 0244; 64R6-NEXT: jr $ra245; 64R6-NEXT: addu $2, $2, $1246;247; 16-LABEL: madd4:248; 16: # %bb.0: # %entry249; 16-NEXT: mult $4, $5250; 16-NEXT: mflo $2251; 16-NEXT: addu $2, $6, $2252; 16-NEXT: jrc $ra253entry:254 %mul = mul nsw i32 %a, %b255 %add = add nsw i32 %c, %mul256 257 ret i32 %add258}259 260define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {261; 32-LABEL: msub1:262; 32: # %bb.0: # %entry263; 32-NEXT: sra $1, $6, 31264; 32-NEXT: mtlo $6265; 32-NEXT: mthi $1266; 32-NEXT: msub $5, $4267; 32-NEXT: mfhi $2268; 32-NEXT: jr $ra269; 32-NEXT: mflo $3270;271; 32R6-LABEL: msub1:272; 32R6: # %bb.0: # %entry273; 32R6-NEXT: mul $1, $5, $4274; 32R6-NEXT: sltu $2, $6, $1275; 32R6-NEXT: muh $3, $5, $4276; 32R6-NEXT: sra $4, $6, 31277; 32R6-NEXT: subu $3, $4, $3278; 32R6-NEXT: subu $2, $3, $2279; 32R6-NEXT: jr $ra280; 32R6-NEXT: subu $3, $6, $1281;282; DSP-LABEL: msub1:283; DSP: # %bb.0: # %entry284; DSP-NEXT: sra $1, $6, 31285; DSP-NEXT: mtlo $6, $ac0286; DSP-NEXT: mthi $1, $ac0287; DSP-NEXT: msub $ac0, $5, $4288; DSP-NEXT: mfhi $2, $ac0289; DSP-NEXT: jr $ra290; DSP-NEXT: mflo $3, $ac0291;292; 64-LABEL: msub1:293; 64: # %bb.0: # %entry294; 64-NEXT: sll $4, $4, 0295; 64-NEXT: sll $5, $5, 0296; 64-NEXT: dmult $5, $4297; 64-NEXT: mflo $1298; 64-NEXT: sll $6, $6, 0299; 64-NEXT: jr $ra300; 64-NEXT: dsubu $2, $6, $1301;302; 64R6-LABEL: msub1:303; 64R6: # %bb.0: # %entry304; 64R6-NEXT: sll $4, $4, 0305; 64R6-NEXT: sll $5, $5, 0306; 64R6-NEXT: dmul $1, $5, $4307; 64R6-NEXT: sll $6, $6, 0308; 64R6-NEXT: jr $ra309; 64R6-NEXT: dsubu $2, $6, $1310;311; 16-LABEL: msub1:312; 16: # %bb.0: # %entry313; 16-NEXT: mult $5, $4314; 16-NEXT: mflo $2315; 16-NEXT: mfhi $4316; 16-NEXT: subu $3, $6, $2317; 16-NEXT: sltu $6, $2318; 16-NEXT: move $2, $24319; 16-NEXT: sra $5, $6, 31320; 16-NEXT: subu $4, $5, $4321; 16-NEXT: subu $2, $4, $2322; 16-NEXT: jrc $ra323entry:324 %conv = sext i32 %c to i64325 %conv2 = sext i32 %a to i64326 %conv4 = sext i32 %b to i64327 %mul = mul nsw i64 %conv4, %conv2328 %sub = sub nsw i64 %conv, %mul329 ret i64 %sub330}331 332define i64 @msub2(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c) nounwind readnone {333; 32-LABEL: msub2:334; 32: # %bb.0: # %entry335; 32-NEXT: addiu $1, $zero, 0336; 32-NEXT: mtlo $6337; 32-NEXT: mthi $1338; 32-NEXT: msubu $5, $4339; 32-NEXT: mfhi $2340; 32-NEXT: jr $ra341; 32-NEXT: mflo $3342;343; 32R6-LABEL: msub2:344; 32R6: # %bb.0: # %entry345; 32R6-NEXT: muhu $1, $5, $4346; 32R6-NEXT: mul $3, $5, $4347; 32R6-NEXT: sltu $2, $6, $3348; 32R6-NEXT: addu $1, $1, $2349; 32R6-NEXT: negu $2, $1350; 32R6-NEXT: jr $ra351; 32R6-NEXT: subu $3, $6, $3352;353; DSP-LABEL: msub2:354; DSP: # %bb.0: # %entry355; DSP-NEXT: addiu $1, $zero, 0356; DSP-NEXT: mtlo $6, $ac0357; DSP-NEXT: mthi $1, $ac0358; DSP-NEXT: msubu $ac0, $5, $4359; DSP-NEXT: mfhi $2, $ac0360; DSP-NEXT: jr $ra361; DSP-NEXT: mflo $3, $ac0362;363; 64-LABEL: msub2:364; 64: # %bb.0: # %entry365; 64-NEXT: dmult $5, $4366; 64-NEXT: mflo $1367; 64-NEXT: jr $ra368; 64-NEXT: dsubu $2, $6, $1369;370; 64R6-LABEL: msub2:371; 64R6: # %bb.0: # %entry372; 64R6-NEXT: dmul $1, $5, $4373; 64R6-NEXT: jr $ra374; 64R6-NEXT: dsubu $2, $6, $1375;376; 16-LABEL: msub2:377; 16: # %bb.0: # %entry378; 16-NEXT: multu $5, $4379; 16-NEXT: mflo $2380; 16-NEXT: mfhi $3381; 16-NEXT: sltu $6, $2382; 16-NEXT: move $4, $24383; 16-NEXT: addu $4, $3, $4384; 16-NEXT: subu $3, $6, $2385; 16-NEXT: neg $2, $4386; 16-NEXT: jrc $ra387entry:388 %conv = zext i32 %c to i64389 %conv2 = zext i32 %a to i64390 %conv4 = zext i32 %b to i64391 %mul = mul nsw i64 %conv4, %conv2392 %sub = sub nsw i64 %conv, %mul393 ret i64 %sub394}395 396define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {397; 32-LABEL: msub3:398; 32: # %bb.0: # %entry399; 32-NEXT: mtlo $7400; 32-NEXT: mthi $6401; 32-NEXT: msub $5, $4402; 32-NEXT: mfhi $2403; 32-NEXT: jr $ra404; 32-NEXT: mflo $3405;406; 32R6-LABEL: msub3:407; 32R6: # %bb.0: # %entry408; 32R6-NEXT: mul $1, $5, $4409; 32R6-NEXT: sltu $2, $7, $1410; 32R6-NEXT: muh $3, $5, $4411; 32R6-NEXT: subu $3, $6, $3412; 32R6-NEXT: subu $2, $3, $2413; 32R6-NEXT: jr $ra414; 32R6-NEXT: subu $3, $7, $1415;416; DSP-LABEL: msub3:417; DSP: # %bb.0: # %entry418; DSP-NEXT: mtlo $7, $ac0419; DSP-NEXT: mthi $6, $ac0420; DSP-NEXT: msub $ac0, $5, $4421; DSP-NEXT: mfhi $2, $ac0422; DSP-NEXT: jr $ra423; DSP-NEXT: mflo $3, $ac0424;425; 64-LABEL: msub3:426; 64: # %bb.0: # %entry427; 64-NEXT: sll $4, $4, 0428; 64-NEXT: sll $5, $5, 0429; 64-NEXT: dmult $5, $4430; 64-NEXT: mflo $1431; 64-NEXT: jr $ra432; 64-NEXT: dsubu $2, $6, $1433;434; 64R6-LABEL: msub3:435; 64R6: # %bb.0: # %entry436; 64R6-NEXT: sll $4, $4, 0437; 64R6-NEXT: sll $5, $5, 0438; 64R6-NEXT: dmul $1, $5, $4439; 64R6-NEXT: jr $ra440; 64R6-NEXT: dsubu $2, $6, $1441;442; 16-LABEL: msub3:443; 16: # %bb.0: # %entry444; 16-NEXT: mult $5, $4445; 16-NEXT: mflo $2446; 16-NEXT: mfhi $4447; 16-NEXT: subu $3, $7, $2448; 16-NEXT: sltu $7, $2449; 16-NEXT: move $2, $24450; 16-NEXT: subu $4, $6, $4451; 16-NEXT: subu $2, $4, $2452; 16-NEXT: jrc $ra453entry:454 %conv = sext i32 %a to i64455 %conv3 = sext i32 %b to i64456 %mul = mul nsw i64 %conv3, %conv457 %sub = sub nsw i64 %c, %mul458 ret i64 %sub459}460 461define i32 @msub4(i32 %a, i32 %b, i32 %c) {462; 32-LABEL: msub4:463; 32: # %bb.0: # %entry464; 32-NEXT: mul $1, $4, $5465; 32-NEXT: jr $ra466; 32-NEXT: subu $2, $6, $1467;468; 32R6-LABEL: msub4:469; 32R6: # %bb.0: # %entry470; 32R6-NEXT: mul $1, $4, $5471; 32R6-NEXT: jr $ra472; 32R6-NEXT: subu $2, $6, $1473;474; DSP-LABEL: msub4:475; DSP: # %bb.0: # %entry476; DSP-NEXT: mul $1, $4, $5477; DSP-NEXT: jr $ra478; DSP-NEXT: subu $2, $6, $1479;480; 64-LABEL: msub4:481; 64: # %bb.0: # %entry482; 64-NEXT: sll $1, $5, 0483; 64-NEXT: sll $2, $4, 0484; 64-NEXT: mul $1, $2, $1485; 64-NEXT: sll $2, $6, 0486; 64-NEXT: jr $ra487; 64-NEXT: subu $2, $2, $1488;489; 64R6-LABEL: msub4:490; 64R6: # %bb.0: # %entry491; 64R6-NEXT: sll $1, $5, 0492; 64R6-NEXT: sll $2, $4, 0493; 64R6-NEXT: mul $1, $2, $1494; 64R6-NEXT: sll $2, $6, 0495; 64R6-NEXT: jr $ra496; 64R6-NEXT: subu $2, $2, $1497;498; 16-LABEL: msub4:499; 16: # %bb.0: # %entry500; 16-NEXT: mult $4, $5501; 16-NEXT: mflo $2502; 16-NEXT: subu $2, $6, $2503; 16-NEXT: jrc $ra504entry:505 %mul = mul nsw i32 %a, %b506 %sub = sub nsw i32 %c, %mul507 508 ret i32 %sub509}510 511define i64 @msub5(i32 %a, i32 %b, i32 %c) {512; 32-LABEL: msub5:513; 32: # %bb.0: # %entry514; 32-NEXT: mult $5, $4515; 32-NEXT: mfhi $1516; 32-NEXT: mflo $3517; 32-NEXT: sltu $2, $3, $6518; 32-NEXT: sra $4, $6, 31519; 32-NEXT: subu $1, $1, $4520; 32-NEXT: subu $2, $1, $2521; 32-NEXT: jr $ra522; 32-NEXT: subu $3, $3, $6523;524; 32R6-LABEL: msub5:525; 32R6: # %bb.0: # %entry526; 32R6-NEXT: mul $1, $5, $4527; 32R6-NEXT: sltu $2, $1, $6528; 32R6-NEXT: muh $3, $5, $4529; 32R6-NEXT: sra $4, $6, 31530; 32R6-NEXT: subu $3, $3, $4531; 32R6-NEXT: subu $2, $3, $2532; 32R6-NEXT: jr $ra533; 32R6-NEXT: subu $3, $1, $6534;535; DSP-LABEL: msub5:536; DSP: # %bb.0: # %entry537; DSP-NEXT: mult $ac0, $5, $4538; DSP-NEXT: mfhi $1, $ac0539; DSP-NEXT: mflo $3, $ac0540; DSP-NEXT: sltu $2, $3, $6541; DSP-NEXT: sra $4, $6, 31542; DSP-NEXT: subu $1, $1, $4543; DSP-NEXT: subu $2, $1, $2544; DSP-NEXT: jr $ra545; DSP-NEXT: subu $3, $3, $6546;547; 64-LABEL: msub5:548; 64: # %bb.0: # %entry549; 64-NEXT: sll $4, $4, 0550; 64-NEXT: sll $5, $5, 0551; 64-NEXT: dmult $5, $4552; 64-NEXT: mflo $1553; 64-NEXT: sll $6, $6, 0554; 64-NEXT: jr $ra555; 64-NEXT: dsubu $2, $1, $6556;557; 64R6-LABEL: msub5:558; 64R6: # %bb.0: # %entry559; 64R6-NEXT: sll $4, $4, 0560; 64R6-NEXT: sll $5, $5, 0561; 64R6-NEXT: dmul $1, $5, $4562; 64R6-NEXT: sll $6, $6, 0563; 64R6-NEXT: jr $ra564; 64R6-NEXT: dsubu $2, $1, $6565;566; 16-LABEL: msub5:567; 16: # %bb.0: # %entry568; 16-NEXT: mult $5, $4569; 16-NEXT: mflo $2570; 16-NEXT: mfhi $4571; 16-NEXT: subu $3, $2, $6572; 16-NEXT: sltu $2, $6573; 16-NEXT: move $2, $24574; 16-NEXT: sra $5, $6, 31575; 16-NEXT: subu $4, $4, $5576; 16-NEXT: subu $2, $4, $2577; 16-NEXT: jrc $ra578entry:579 %conv = sext i32 %a to i64580 %conv3 = sext i32 %b to i64581 %conv4 = sext i32 %c to i64582 %mul = mul nsw i64 %conv3, %conv583 %sub = sub nsw i64 %mul, %conv4584 ret i64 %sub585}586