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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst < %s |\3; RUN: FileCheck %s -check-prefixes=MMR24; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+dsp,+micromips -asm-show-inst < %s |\5; RUN: FileCheck %s -check-prefixes=MMR2-DSP6 7define i64 @test(i32 signext %a, i32 signext %b) {8; MMR2-LABEL: test:9; MMR2: # %bb.0: # %entry10; MMR2-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM11; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>12; MMR2-NEXT: # <MCOperand Imm:0>>13; MMR2-NEXT: li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM14; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>15; MMR2-NEXT: # <MCOperand Imm:1>>16; MMR2-NEXT: mtlo $3 # <MCInst #{{[0-9]+}} MTLO_MM17; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>18; MMR2-NEXT: mthi $2 # <MCInst #{{[0-9]+}} MTHI_MM19; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>20; MMR2-NEXT: madd $4, $5 # <MCInst #{{[0-9]+}} MADD21; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>22; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>23; MMR2-NEXT: mflo16 $2 # <MCInst #{{[0-9]+}} MFLO16_MM24; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>25; MMR2-NEXT: mfhi16 $3 # <MCInst #{{[0-9]+}} MFHI16_MM26; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>27; MMR2-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM28; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>29;30; MMR2-DSP-LABEL: test:31; MMR2-DSP: # %bb.0: # %entry32; MMR2-DSP-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM33; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>34; MMR2-DSP-NEXT: # <MCOperand Imm:0>>35; MMR2-DSP-NEXT: li16 $3, 1 # <MCInst #{{[0-9]+}} LI16_MM36; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>37; MMR2-DSP-NEXT: # <MCOperand Imm:1>>38; MMR2-DSP-NEXT: mtlo $3, $ac0 # <MCInst #{{[0-9]+}} MTLO_DSP39; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>40; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>41; MMR2-DSP-NEXT: mthi $2, $ac0 # <MCInst #{{[0-9]+}} MTHI_DSP42; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>43; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>44; MMR2-DSP-NEXT: madd $ac0, $4, $5 # <MCInst #{{[0-9]+}} MADD_DSP45; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>46; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>47; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>48; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>49; MMR2-DSP-NEXT: mflo $2, $ac0 # <MCInst #{{[0-9]+}} MFLO_DSP50; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>51; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>52; MMR2-DSP-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM53; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>54; MMR2-DSP-NEXT: mfhi $3, $ac0 # <MCInst #{{[0-9]+}} MFHI_DSP55; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>56; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>>57entry:58 %conv = sext i32 %a to i6459 %conv1 = sext i32 %b to i6460 %mul = mul nsw i64 %conv, %conv161 %add = add nsw i64 %mul, 162 ret i64 %add63}64