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1; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \2; RUN: -relocation-model=pic -O3 < %s | FileCheck %s3; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -mattr=+micromips \4; RUN: -relocation-model=pic -O3 < %s | FileCheck %s5 6@a = global i32 10, align 47@b = global i32 0, align 48@c = global i32 10, align 49@d = global i32 0, align 410 11define i32 @shift_left() nounwind {12entry:13 %0 = load i32, ptr @a, align 414 %shl = shl i32 %0, 415 store i32 %shl, ptr @b, align 416 17 %1 = load i32, ptr @c, align 418 %shl1 = shl i32 %1, 1019 store i32 %shl1, ptr @d, align 420 21 ret i32 022}23 24; CHECK: sll16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}}25; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}26 27@i = global i32 10654, align 428@j = global i32 0, align 429@m = global i32 10, align 430@n = global i32 0, align 431 32define i32 @shift_right() nounwind {33entry:34 %0 = load i32, ptr @i, align 435 %shr = lshr i32 %0, 436 store i32 %shr, ptr @j, align 437 38 %1 = load i32, ptr @m, align 439 %shr1 = lshr i32 %1, 1040 store i32 %shr1, ptr @n, align 441 42 ret i32 043}44 45; CHECK: srl16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}}46; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}47