216 lines · plain
1; RUN: llc -mtriple=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MIPS4,ACCMULDIV %s2; RUN: llc -mtriple=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s3; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s4; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,GPRMULDIV %s5 6@gll0 = common global i64 0, align 87@gll1 = common global i64 0, align 88 9define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {10entry:11; ALL-LABEL: f0:12; ALL: daddu $2, ${{[45]}}, ${{[45]}}13 %add = add nsw i64 %a1, %a014 ret i64 %add15}16 17define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {18entry:19; ALL-LABEL: f1:20; ALL: dsubu $2, $4, $521 %sub = sub nsw i64 %a0, %a122 ret i64 %sub23}24 25define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {26entry:27; ALL-LABEL: f4:28; ALL: and $2, ${{[45]}}, ${{[45]}}29 %and = and i64 %a1, %a030 ret i64 %and31}32 33define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {34entry:35; ALL-LABEL: f5:36; ALL: or $2, ${{[45]}}, ${{[45]}}37 %or = or i64 %a1, %a038 ret i64 %or39}40 41define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {42entry:43; ALL-LABEL: f6:44; ALL: xor $2, ${{[45]}}, ${{[45]}}45 %xor = xor i64 %a1, %a046 ret i64 %xor47}48 49define i64 @f7(i64 %a0) nounwind readnone {50entry:51; ALL-LABEL: f7:52; ALL: daddiu $2, $4, 2053 %add = add nsw i64 %a0, 2054 ret i64 %add55}56 57define i64 @f8(i64 %a0) nounwind readnone {58entry:59; ALL-LABEL: f8:60; ALL: daddiu $2, $4, -2061 %sub = add nsw i64 %a0, -2062 ret i64 %sub63}64 65define i64 @f9(i64 %a0) nounwind readnone {66entry:67; ALL-LABEL: f9:68; ALL: andi $2, $4, 2069 %and = and i64 %a0, 2070 ret i64 %and71}72 73define i64 @f10(i64 %a0) nounwind readnone {74entry:75; ALL-LABEL: f10:76; ALL: ori $2, $4, 2077 %or = or i64 %a0, 2078 ret i64 %or79}80 81define i64 @f11(i64 %a0) nounwind readnone {82entry:83; ALL-LABEL: f11:84; ALL: xori $2, $4, 2085 %xor = xor i64 %a0, 2086 ret i64 %xor87}88 89define i64 @f12(i64 %a, i64 %b) nounwind readnone {90entry:91; ALL-LABEL: f12:92 93; ACCMULDIV: mult ${{[45]}}, ${{[45]}}94; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}95 96 %mul = mul nsw i64 %b, %a97 ret i64 %mul98}99 100define i64 @f13(i64 %a, i64 %b) nounwind readnone {101entry:102; ALL-LABEL: f13:103 104; ACCMULDIV: mult ${{[45]}}, ${{[45]}}105; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}106 107 %mul = mul i64 %b, %a108 ret i64 %mul109}110 111define i64 @f14(i64 %a, i64 %b) nounwind readnone {112entry:113; ALL-LABEL: f14:114; ALL-DAG: ld $[[T0:[0-9]+]], %lo(gll0)(${{[0-9]+}})115; ALL-DAG: ld $[[T1:[0-9]+]], %lo(gll1)(${{[0-9]+}})116 117; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]118; ACCMULDIV: teq $[[T1]], $zero, 7119; ACCMULDIV: mflo $2120 121; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]122; GPRMULDIV: teq $[[T1]], $zero, 7123 124 %0 = load i64, ptr @gll0, align 8125 %1 = load i64, ptr @gll1, align 8126 %div = sdiv i64 %0, %1127 ret i64 %div128}129 130define i64 @f15() nounwind readnone {131entry:132; ALL-LABEL: f15:133; ALL-DAG: ld $[[T0:[0-9]+]], %lo(gll0)(${{[0-9]+}})134; ALL-DAG: ld $[[T1:[0-9]+]], %lo(gll1)(${{[0-9]+}})135 136; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]137; ACCMULDIV: teq $[[T1]], $zero, 7138; ACCMULDIV: mflo $2139 140; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]141; GPRMULDIV: teq $[[T1]], $zero, 7142 143 %0 = load i64, ptr @gll0, align 8144 %1 = load i64, ptr @gll1, align 8145 %div = udiv i64 %0, %1146 ret i64 %div147}148 149define i64 @f16(i64 %a, i64 %b) nounwind readnone {150entry:151; ALL-LABEL: f16:152 153; ACCMULDIV: ddiv $zero, $4, $5154; ACCMULDIV: teq $5, $zero, 7155; ACCMULDIV: mfhi $2156 157; GPRMULDIV: dmod $2, $4, $5158; GPRMULDIV: teq $5, $zero, 7159 160 %rem = srem i64 %a, %b161 ret i64 %rem162}163 164define i64 @f17(i64 %a, i64 %b) nounwind readnone {165entry:166; ALL-LABEL: f17:167 168; ACCMULDIV: ddivu $zero, $4, $5169; ACCMULDIV: teq $5, $zero, 7170; ACCMULDIV: mfhi $2171 172; GPRMULDIV: dmodu $2, $4, $5173; GPRMULDIV: teq $5, $zero, 7174 175 %rem = urem i64 %a, %b176 ret i64 %rem177}178 179declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone180 181define i64 @f18(i64 %X) nounwind readnone {182entry:183; ALL-LABEL: f18:184 185; The MIPS4 version is too long to reasonably test. At least check we don't get dclz186; MIPS4-NOT: dclz187 188; HAS-DCLO: dclz $2, $4189 190 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)191 ret i64 %tmp1192}193 194define i64 @f19(i64 %X) nounwind readnone {195entry:196; ALL-LABEL: f19:197 198; The MIPS4 version is too long to reasonably test. At least check we don't get dclo199; MIPS4-NOT: dclo200 201; HAS-DCLO: dclo $2, $4202 203 %neg = xor i64 %X, -1204 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)205 ret i64 %tmp1206}207 208define i64 @f20(i64 %a, i64 %b) nounwind readnone {209entry:210; ALL-LABEL: f20:211; ALL: nor $2, ${{[45]}}, ${{[45]}}212 %or = or i64 %b, %a213 %neg = xor i64 %or, -1214 ret i64 %neg215}216