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1; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,ACC2; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,ACC3; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC4; RUN: llc -mtriple=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR5 6; FileCheck prefixes:7; ALL - All targets8; ACC - Targets with accumulator based mul/div (i.e. pre-MIPS32r6)9; GPR - Targets with register based mul/div (i.e. MIPS32r6)10 11define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {12entry:13; ALL-LABEL: m0:14; ACC: dmult ${{[45]}}, ${{[45]}}15; ACC: mflo $216; GPR: dmul $2, ${{[45]}}, ${{[45]}}17 %mul = mul i64 %a1, %a018 ret i64 %mul19}20 21define i64 @m1(i64 %a) nounwind readnone {22entry:23; ALL-LABEL: m1:24; ALL: lui $[[T0:[0-9]+]], 2184525; ALL: addiu $[[T0]], $[[T0]], 2184526; ALL: dsll $[[T0]], $[[T0]], 1627; ALL: addiu $[[T0]], $[[T0]], 2184528; ALL: dsll $[[T0]], $[[T0]], 1629; ALL: addiu $[[T0]], $[[T0]], 2184630 31; ACC: dmult $4, $[[T0]]32; ACC: mfhi $[[T1:[0-9]+]]33; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]34 35; ALL: dsrl $2, $[[T1]], 6336; ALL: daddu $2, $[[T1]], $237 %div = sdiv i64 %a, 338 ret i64 %div39}40 41define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {42entry:43; ALL-LABEL: d0:44; ACC: ddivu $zero, $4, $545; ACC: mflo $246; GPR: ddivu $2, $4, $547 %div = udiv i64 %a0, %a148 ret i64 %div49}50 51define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {52entry:53; ALL-LABEL: d1:54; ACC: ddiv $zero, $4, $555; ACC: mflo $256; GPR: ddiv $2, $4, $557 %div = sdiv i64 %a0, %a158 ret i64 %div59}60 61define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {62entry:63; ALL-LABEL: d2:64; ACC: ddivu $zero, $4, $565; ACC: mfhi $266; GPR: dmodu $2, $4, $567 %rem = urem i64 %a0, %a168 ret i64 %rem69}70 71define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {72entry:73; ALL-LABEL: d3:74; ACC: ddiv $zero, $4, $575; ACC: mfhi $276; GPR: dmod $2, $4, $577 %rem = srem i64 %a0, %a178 ret i64 %rem79}80