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1; Test the MSA intrinsics that are encoded with the 2R instruction format.2 3; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s4; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s5 6@llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 167@llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 168 9define void @llvm_mips_nloc_b_test() nounwind {10entry:11 %0 = load <16 x i8>, ptr @llvm_mips_nloc_b_ARG112 %1 = tail call <16 x i8> @llvm.mips.nloc.b(<16 x i8> %0)13 store <16 x i8> %1, ptr @llvm_mips_nloc_b_RES14 ret void15}16 17declare <16 x i8> @llvm.mips.nloc.b(<16 x i8>) nounwind18 19; CHECK: llvm_mips_nloc_b_test:20; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nloc_b_ARG1)21; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])22; CHECK-DAG: nloc.b [[WD:\$w[0-9]+]], [[WS]]23; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nloc_b_RES)24; CHECK-DAG: st.b [[WD]], 0([[R2]])25; CHECK: .size llvm_mips_nloc_b_test26;27@llvm_mips_nloc_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1628@llvm_mips_nloc_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1629 30define void @llvm_mips_nloc_h_test() nounwind {31entry:32 %0 = load <8 x i16>, ptr @llvm_mips_nloc_h_ARG133 %1 = tail call <8 x i16> @llvm.mips.nloc.h(<8 x i16> %0)34 store <8 x i16> %1, ptr @llvm_mips_nloc_h_RES35 ret void36}37 38declare <8 x i16> @llvm.mips.nloc.h(<8 x i16>) nounwind39 40; CHECK: llvm_mips_nloc_h_test:41; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nloc_h_ARG1)42; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])43; CHECK-DAG: nloc.h [[WD:\$w[0-9]+]], [[WS]]44; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nloc_h_RES)45; CHECK-DAG: st.h [[WD]], 0([[R2]])46; CHECK: .size llvm_mips_nloc_h_test47;48@llvm_mips_nloc_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1649@llvm_mips_nloc_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1650 51define void @llvm_mips_nloc_w_test() nounwind {52entry:53 %0 = load <4 x i32>, ptr @llvm_mips_nloc_w_ARG154 %1 = tail call <4 x i32> @llvm.mips.nloc.w(<4 x i32> %0)55 store <4 x i32> %1, ptr @llvm_mips_nloc_w_RES56 ret void57}58 59declare <4 x i32> @llvm.mips.nloc.w(<4 x i32>) nounwind60 61; CHECK: llvm_mips_nloc_w_test:62; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nloc_w_ARG1)63; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])64; CHECK-DAG: nloc.w [[WD:\$w[0-9]+]], [[WS]]65; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nloc_w_RES)66; CHECK-DAG: st.w [[WD]], 0([[R2]])67; CHECK: .size llvm_mips_nloc_w_test68;69@llvm_mips_nloc_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1670@llvm_mips_nloc_d_RES = global <2 x i64> <i64 0, i64 0>, align 1671 72define void @llvm_mips_nloc_d_test() nounwind {73entry:74 %0 = load <2 x i64>, ptr @llvm_mips_nloc_d_ARG175 %1 = tail call <2 x i64> @llvm.mips.nloc.d(<2 x i64> %0)76 store <2 x i64> %1, ptr @llvm_mips_nloc_d_RES77 ret void78}79 80declare <2 x i64> @llvm.mips.nloc.d(<2 x i64>) nounwind81 82; CHECK: llvm_mips_nloc_d_test:83; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nloc_d_ARG1)84; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])85; CHECK-DAG: nloc.d [[WD:\$w[0-9]+]], [[WS]]86; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nloc_d_RES)87; CHECK-DAG: st.d [[WD]], 0([[R2]])88; CHECK: .size llvm_mips_nloc_d_test89;90@llvm_mips_nlzc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 1691@llvm_mips_nlzc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1692 93define void @llvm_mips_nlzc_b_test() nounwind {94entry:95 %0 = load <16 x i8>, ptr @llvm_mips_nlzc_b_ARG196 %1 = tail call <16 x i8> @llvm.mips.nlzc.b(<16 x i8> %0)97 store <16 x i8> %1, ptr @llvm_mips_nlzc_b_RES98 ret void99}100 101declare <16 x i8> @llvm.mips.nlzc.b(<16 x i8>) nounwind102 103; CHECK: llvm_mips_nlzc_b_test:104; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nlzc_b_ARG1)105; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])106; CHECK-DAG: nlzc.b [[WD:\$w[0-9]+]], [[WS]]107; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nlzc_b_RES)108; CHECK-DAG: st.b [[WD]], 0([[R2]])109; CHECK: .size llvm_mips_nlzc_b_test110;111@llvm_mips_nlzc_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16112@llvm_mips_nlzc_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16113 114define void @llvm_mips_nlzc_h_test() nounwind {115entry:116 %0 = load <8 x i16>, ptr @llvm_mips_nlzc_h_ARG1117 %1 = tail call <8 x i16> @llvm.mips.nlzc.h(<8 x i16> %0)118 store <8 x i16> %1, ptr @llvm_mips_nlzc_h_RES119 ret void120}121 122declare <8 x i16> @llvm.mips.nlzc.h(<8 x i16>) nounwind123 124; CHECK: llvm_mips_nlzc_h_test:125; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nlzc_h_ARG1)126; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])127; CHECK-DAG: nlzc.h [[WD:\$w[0-9]+]], [[WS]]128; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nlzc_h_RES)129; CHECK-DAG: st.h [[WD]], 0([[R2]])130; CHECK: .size llvm_mips_nlzc_h_test131;132@llvm_mips_nlzc_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16133@llvm_mips_nlzc_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16134 135define void @llvm_mips_nlzc_w_test() nounwind {136entry:137 %0 = load <4 x i32>, ptr @llvm_mips_nlzc_w_ARG1138 %1 = tail call <4 x i32> @llvm.mips.nlzc.w(<4 x i32> %0)139 store <4 x i32> %1, ptr @llvm_mips_nlzc_w_RES140 ret void141}142 143declare <4 x i32> @llvm.mips.nlzc.w(<4 x i32>) nounwind144 145; CHECK: llvm_mips_nlzc_w_test:146; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nlzc_w_ARG1)147; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])148; CHECK-DAG: nlzc.w [[WD:\$w[0-9]+]], [[WS]]149; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nlzc_w_RES)150; CHECK-DAG: st.w [[WD]], 0([[R2]])151; CHECK: .size llvm_mips_nlzc_w_test152;153@llvm_mips_nlzc_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16154@llvm_mips_nlzc_d_RES = global <2 x i64> <i64 0, i64 0>, align 16155 156define void @llvm_mips_nlzc_d_test() nounwind {157entry:158 %0 = load <2 x i64>, ptr @llvm_mips_nlzc_d_ARG1159 %1 = tail call <2 x i64> @llvm.mips.nlzc.d(<2 x i64> %0)160 store <2 x i64> %1, ptr @llvm_mips_nlzc_d_RES161 ret void162}163 164declare <2 x i64> @llvm.mips.nlzc.d(<2 x i64>) nounwind165 166; CHECK: llvm_mips_nlzc_d_test:167; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_nlzc_d_ARG1)168; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])169; CHECK-DAG: nlzc.d [[WD:\$w[0-9]+]], [[WS]]170; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_nlzc_d_RES)171; CHECK-DAG: st.d [[WD]], 0([[R2]])172; CHECK: .size llvm_mips_nlzc_d_test173;174@llvm_mips_pcnt_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16175@llvm_mips_pcnt_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16176 177define void @llvm_mips_pcnt_b_test() nounwind {178entry:179 %0 = load <16 x i8>, ptr @llvm_mips_pcnt_b_ARG1180 %1 = tail call <16 x i8> @llvm.mips.pcnt.b(<16 x i8> %0)181 store <16 x i8> %1, ptr @llvm_mips_pcnt_b_RES182 ret void183}184 185declare <16 x i8> @llvm.mips.pcnt.b(<16 x i8>) nounwind186 187; CHECK: llvm_mips_pcnt_b_test:188; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_pcnt_b_ARG1)189; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])190; CHECK-DAG: pcnt.b [[WD:\$w[0-9]+]], [[WS]]191; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_pcnt_b_RES)192; CHECK-DAG: st.b [[WD]], 0([[R2]])193; CHECK: .size llvm_mips_pcnt_b_test194;195@llvm_mips_pcnt_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16196@llvm_mips_pcnt_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16197 198define void @llvm_mips_pcnt_h_test() nounwind {199entry:200 %0 = load <8 x i16>, ptr @llvm_mips_pcnt_h_ARG1201 %1 = tail call <8 x i16> @llvm.mips.pcnt.h(<8 x i16> %0)202 store <8 x i16> %1, ptr @llvm_mips_pcnt_h_RES203 ret void204}205 206declare <8 x i16> @llvm.mips.pcnt.h(<8 x i16>) nounwind207 208; CHECK: llvm_mips_pcnt_h_test:209; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_pcnt_h_ARG1)210; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])211; CHECK-DAG: pcnt.h [[WD:\$w[0-9]+]], [[WS]]212; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_pcnt_h_RES)213; CHECK-DAG: st.h [[WD]], 0([[R2]])214; CHECK: .size llvm_mips_pcnt_h_test215;216@llvm_mips_pcnt_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16217@llvm_mips_pcnt_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16218 219define void @llvm_mips_pcnt_w_test() nounwind {220entry:221 %0 = load <4 x i32>, ptr @llvm_mips_pcnt_w_ARG1222 %1 = tail call <4 x i32> @llvm.mips.pcnt.w(<4 x i32> %0)223 store <4 x i32> %1, ptr @llvm_mips_pcnt_w_RES224 ret void225}226 227declare <4 x i32> @llvm.mips.pcnt.w(<4 x i32>) nounwind228 229; CHECK: llvm_mips_pcnt_w_test:230; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_pcnt_w_ARG1)231; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])232; CHECK-DAG: pcnt.w [[WD:\$w[0-9]+]], [[WS]]233; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_pcnt_w_RES)234; CHECK-DAG: st.w [[WD]], 0([[R2]])235; CHECK: .size llvm_mips_pcnt_w_test236;237@llvm_mips_pcnt_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16238@llvm_mips_pcnt_d_RES = global <2 x i64> <i64 0, i64 0>, align 16239 240define void @llvm_mips_pcnt_d_test() nounwind {241entry:242 %0 = load <2 x i64>, ptr @llvm_mips_pcnt_d_ARG1243 %1 = tail call <2 x i64> @llvm.mips.pcnt.d(<2 x i64> %0)244 store <2 x i64> %1, ptr @llvm_mips_pcnt_d_RES245 ret void246}247 248declare <2 x i64> @llvm.mips.pcnt.d(<2 x i64>) nounwind249 250; CHECK: llvm_mips_pcnt_d_test:251; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_pcnt_d_ARG1)252; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])253; CHECK-DAG: pcnt.d [[WD:\$w[0-9]+]], [[WS]]254; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_pcnt_d_RES)255; CHECK-DAG: st.d [[WD]], 0([[R2]])256; CHECK: .size llvm_mips_pcnt_d_test257;258