100 lines · plain
1; Test the MSA intrinsics that are encoded with the 2R instruction format and2; convert scalars to vectors.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \5; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS326; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \7; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS328; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \9; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS6410; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \11; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS6412 13@llvm_mips_fill_b_ARG1 = global i32 23, align 1614@llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 1615 16define void @llvm_mips_fill_b_test() nounwind {17entry:18 %0 = load i32, ptr @llvm_mips_fill_b_ARG119 %1 = tail call <16 x i8> @llvm.mips.fill.b(i32 %0)20 store <16 x i8> %1, ptr @llvm_mips_fill_b_RES21 ret void22}23 24declare <16 x i8> @llvm.mips.fill.b(i32) nounwind25 26; MIPS-ANY: llvm_mips_fill_b_test:27; MIPS32-DAG: lw [[R1:\$[0-9]+]],28; MIPS64-DAG: ld [[R1:\$[0-9]+]],29; MIPS-ANY-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]30; MIPS-ANY-DAG: st.b [[R2]],31; MIPS-ANY: .size llvm_mips_fill_b_test32;33@llvm_mips_fill_h_ARG1 = global i32 23, align 1634@llvm_mips_fill_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 1635 36define void @llvm_mips_fill_h_test() nounwind {37entry:38 %0 = load i32, ptr @llvm_mips_fill_h_ARG139 %1 = tail call <8 x i16> @llvm.mips.fill.h(i32 %0)40 store <8 x i16> %1, ptr @llvm_mips_fill_h_RES41 ret void42}43 44declare <8 x i16> @llvm.mips.fill.h(i32) nounwind45 46; MIPS-ANY: llvm_mips_fill_h_test:47; MIPS32-DAG: lw [[R1:\$[0-9]+]],48; MIPS64-DAG: ld [[R1:\$[0-9]+]],49; MIPS-ANY-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]50; MIPS-ANY-DAG: st.h [[R2]],51; MIPS-ANY: .size llvm_mips_fill_h_test52;53@llvm_mips_fill_w_ARG1 = global i32 23, align 1654@llvm_mips_fill_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1655 56define void @llvm_mips_fill_w_test() nounwind {57entry:58 %0 = load i32, ptr @llvm_mips_fill_w_ARG159 %1 = tail call <4 x i32> @llvm.mips.fill.w(i32 %0)60 store <4 x i32> %1, ptr @llvm_mips_fill_w_RES61 ret void62}63 64declare <4 x i32> @llvm.mips.fill.w(i32) nounwind65 66; MIPS-ANY: llvm_mips_fill_w_test:67; MIPS32-DAG: lw [[R1:\$[0-9]+]],68; MIPS64-DAG: ld [[R1:\$[0-9]+]],69; MIPS-ANY-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]70; MIPS-ANY-DAG: st.w [[R2]],71; MIPS-ANY: .size llvm_mips_fill_w_test72;73@llvm_mips_fill_d_ARG1 = global i64 23, align 1674@llvm_mips_fill_d_RES = global <2 x i64> <i64 0, i64 0>, align 1675 76define void @llvm_mips_fill_d_test() nounwind {77entry:78 %0 = load i64, ptr @llvm_mips_fill_d_ARG179 %1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0)80 store <2 x i64> %1, ptr @llvm_mips_fill_d_RES81 ret void82}83 84declare <2 x i64> @llvm.mips.fill.d(i64) nounwind85 86; MIPS-ANY: llvm_mips_fill_d_test:87; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0(88; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4(89; MIPS64-DAG: ld [[R1]], %got_disp(llvm_mips_fill_d_ARG1)90; MIPS32-DAG: insert.w [[R3:\$w[0-9]+]][0], [[R1]]91; MIPS32-DAG: insert.w [[R3]][1], [[R2]]92; MIPS32-DAG: insert.w [[R3]][2], [[R1]]93; MIPS32-DAG: insert.w [[R3]][3], [[R2]]94; MIPS64-DAG: fill.d [[WD:\$w[0-9]+]], [[R1]]95; MIPS32-DAG: st.w [[R3]],96; MIPS64-DAG: ld [[RD:\$[0-9]+]], %got_disp(llvm_mips_fill_d_RES)97; MIPS64-DAG: st.d [[WD]], 0([[RD]])98; MIPS-ANY: .size llvm_mips_fill_d_test99;100