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1; Test the MSA integer to floating point conversion intrinsics that are encoded2; with the 2RF instruction format.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s6 7@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 168@llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 169 10define void @llvm_mips_ffint_s_w_test() nounwind {11entry:12 %0 = load <4 x i32>, ptr @llvm_mips_ffint_s_w_ARG113 %1 = tail call <4 x float> @llvm.mips.ffint.s.w(<4 x i32> %0)14 store <4 x float> %1, ptr @llvm_mips_ffint_s_w_RES15 ret void16}17 18declare <4 x float> @llvm.mips.ffint.s.w(<4 x i32>) nounwind19 20; CHECK: llvm_mips_ffint_s_w_test:21; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_s_w_ARG1)22; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])23; CHECK-DAG: ffint_s.w [[WD:\$w[0-9]+]], [[WS]]24; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_s_w_RES)25; CHECK-DAG: st.w [[WD]], 0([[R2]])26; CHECK: .size llvm_mips_ffint_s_w_test27;28@llvm_mips_ffint_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1629@llvm_mips_ffint_s_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 1630 31define void @llvm_mips_ffint_s_d_test() nounwind {32entry:33 %0 = load <2 x i64>, ptr @llvm_mips_ffint_s_d_ARG134 %1 = tail call <2 x double> @llvm.mips.ffint.s.d(<2 x i64> %0)35 store <2 x double> %1, ptr @llvm_mips_ffint_s_d_RES36 ret void37}38 39declare <2 x double> @llvm.mips.ffint.s.d(<2 x i64>) nounwind40 41; CHECK: llvm_mips_ffint_s_d_test:42; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_s_d_ARG1)43; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])44; CHECK-DAG: ffint_s.d [[WD:\$w[0-9]+]], [[WS]]45; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_s_d_RES)46; CHECK-DAG: st.d [[WD]], 0([[R2]])47; CHECK: .size llvm_mips_ffint_s_d_test48;49@llvm_mips_ffint_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1650@llvm_mips_ffint_u_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 1651 52define void @llvm_mips_ffint_u_w_test() nounwind {53entry:54 %0 = load <4 x i32>, ptr @llvm_mips_ffint_u_w_ARG155 %1 = tail call <4 x float> @llvm.mips.ffint.u.w(<4 x i32> %0)56 store <4 x float> %1, ptr @llvm_mips_ffint_u_w_RES57 ret void58}59 60declare <4 x float> @llvm.mips.ffint.u.w(<4 x i32>) nounwind61 62; CHECK: llvm_mips_ffint_u_w_test:63; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_u_w_ARG1)64; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])65; CHECK-DAG: ffint_u.w [[WD:\$w[0-9]+]], [[WS]]66; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_u_w_RES)67; CHECK-DAG: st.w [[WD]], 0([[R2]])68; CHECK: .size llvm_mips_ffint_u_w_test69;70@llvm_mips_ffint_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 1671@llvm_mips_ffint_u_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 1672 73define void @llvm_mips_ffint_u_d_test() nounwind {74entry:75 %0 = load <2 x i64>, ptr @llvm_mips_ffint_u_d_ARG176 %1 = tail call <2 x double> @llvm.mips.ffint.u.d(<2 x i64> %0)77 store <2 x double> %1, ptr @llvm_mips_ffint_u_d_RES78 ret void79}80 81declare <2 x double> @llvm.mips.ffint.u.d(<2 x i64>) nounwind82 83; CHECK: llvm_mips_ffint_u_d_test:84; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_u_d_ARG1)85; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])86; CHECK-DAG: ffint_u.d [[WD:\$w[0-9]+]], [[WS]]87; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_u_d_RES)88; CHECK-DAG: st.d [[WD]], 0([[R2]])89; CHECK: .size llvm_mips_ffint_u_d_test90;91