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1; Test the MSA fixed-point to floating point conversion intrinsics that are2; encoded with the 2RF instruction format.3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s6 7@llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 168@llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 169 10define void @llvm_mips_ffql_w_test() nounwind {11entry:12 %0 = load <8 x i16>, ptr @llvm_mips_ffql_w_ARG113 %1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0)14 store <4 x float> %1, ptr @llvm_mips_ffql_w_RES15 ret void16}17 18declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind19 20; CHECK: llvm_mips_ffql_w_test:21; CHECK: ld.h22; CHECK: ffql.w23; CHECK: st.w24; CHECK: .size llvm_mips_ffql_w_test25;26@llvm_mips_ffql_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1627@llvm_mips_ffql_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 1628 29define void @llvm_mips_ffql_d_test() nounwind {30entry:31 %0 = load <4 x i32>, ptr @llvm_mips_ffql_d_ARG132 %1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0)33 store <2 x double> %1, ptr @llvm_mips_ffql_d_RES34 ret void35}36 37declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind38 39; CHECK: llvm_mips_ffql_d_test:40; CHECK: ld.w41; CHECK: ffql.d42; CHECK: st.d43; CHECK: .size llvm_mips_ffql_d_test44;45@llvm_mips_ffqr_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 1646@llvm_mips_ffqr_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 1647 48define void @llvm_mips_ffqr_w_test() nounwind {49entry:50 %0 = load <8 x i16>, ptr @llvm_mips_ffqr_w_ARG151 %1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0)52 store <4 x float> %1, ptr @llvm_mips_ffqr_w_RES53 ret void54}55 56declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind57 58; CHECK: llvm_mips_ffqr_w_test:59; CHECK: ld.h60; CHECK: ffqr.w61; CHECK: st.w62; CHECK: .size llvm_mips_ffqr_w_test63;64@llvm_mips_ffqr_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 1665@llvm_mips_ffqr_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 1666 67define void @llvm_mips_ffqr_d_test() nounwind {68entry:69 %0 = load <4 x i32>, ptr @llvm_mips_ffqr_d_ARG170 %1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0)71 store <2 x double> %1, ptr @llvm_mips_ffqr_d_RES72 ret void73}74 75declare <2 x double> @llvm.mips.ffqr.d(<4 x i32>) nounwind76 77; CHECK: llvm_mips_ffqr_d_test:78; CHECK: ld.w79; CHECK: ffqr.d80; CHECK: st.d81; CHECK: .size llvm_mips_ffqr_d_test82;83