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1; Test the MSA floating point to integer intrinsics that are encoded with the2; 2RF instruction format. This includes conversions but other instructions such3; as fclass are also here.4 5; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s6; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s7 8@llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 169@llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1610 11define void @llvm_mips_fclass_w_test() nounwind {12entry:13 %0 = load <4 x float>, ptr @llvm_mips_fclass_w_ARG114 %1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0)15 store <4 x i32> %1, ptr @llvm_mips_fclass_w_RES16 ret void17}18 19declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind20 21; CHECK: llvm_mips_fclass_w_test:22; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_fclass_w_ARG1)23; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])24; CHECK-DAG: fclass.w [[WD:\$w[0-9]+]], [[WS]]25; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_fclass_w_RES)26; CHECK-DAG: st.w [[WD]], 0([[R2]])27; CHECK: .size llvm_mips_fclass_w_test28;29@llvm_mips_fclass_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1630@llvm_mips_fclass_d_RES = global <2 x i64> <i64 0, i64 0>, align 1631 32define void @llvm_mips_fclass_d_test() nounwind {33entry:34 %0 = load <2 x double>, ptr @llvm_mips_fclass_d_ARG135 %1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0)36 store <2 x i64> %1, ptr @llvm_mips_fclass_d_RES37 ret void38}39 40declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind41 42; CHECK: llvm_mips_fclass_d_test:43; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_fclass_d_ARG1)44; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])45; CHECK-DAG: fclass.d [[WD:\$w[0-9]+]], [[WS]]46; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_fclass_d_RES)47; CHECK-DAG: st.d [[WD]], 0([[R2]])48; CHECK: .size llvm_mips_fclass_d_test49;50@llvm_mips_ftrunc_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 1651@llvm_mips_ftrunc_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1652 53define void @llvm_mips_ftrunc_s_w_test() nounwind {54entry:55 %0 = load <4 x float>, ptr @llvm_mips_ftrunc_s_w_ARG156 %1 = tail call <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float> %0)57 store <4 x i32> %1, ptr @llvm_mips_ftrunc_s_w_RES58 ret void59}60 61declare <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float>) nounwind62 63; CHECK: llvm_mips_ftrunc_s_w_test:64; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_s_w_ARG1)65; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])66; CHECK-DAG: ftrunc_s.w [[WD:\$w[0-9]+]], [[WS]]67; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_s_w_RES)68; CHECK-DAG: st.w [[WD]], 0([[R2]])69; CHECK: .size llvm_mips_ftrunc_s_w_test70;71@llvm_mips_ftrunc_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 1672@llvm_mips_ftrunc_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 1673 74define void @llvm_mips_ftrunc_s_d_test() nounwind {75entry:76 %0 = load <2 x double>, ptr @llvm_mips_ftrunc_s_d_ARG177 %1 = tail call <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double> %0)78 store <2 x i64> %1, ptr @llvm_mips_ftrunc_s_d_RES79 ret void80}81 82declare <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double>) nounwind83 84; CHECK: llvm_mips_ftrunc_s_d_test:85; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_s_d_ARG1)86; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])87; CHECK-DAG: ftrunc_s.d [[WD:\$w[0-9]+]], [[WS]]88; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_s_d_RES)89; CHECK-DAG: st.d [[WD]], 0([[R2]])90; CHECK: .size llvm_mips_ftrunc_s_d_test91;92@llvm_mips_ftrunc_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 1693@llvm_mips_ftrunc_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 1694 95define void @llvm_mips_ftrunc_u_w_test() nounwind {96entry:97 %0 = load <4 x float>, ptr @llvm_mips_ftrunc_u_w_ARG198 %1 = tail call <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float> %0)99 store <4 x i32> %1, ptr @llvm_mips_ftrunc_u_w_RES100 ret void101}102 103declare <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float>) nounwind104 105; CHECK: llvm_mips_ftrunc_u_w_test:106; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_u_w_ARG1)107; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])108; CHECK-DAG: ftrunc_u.w [[WD:\$w[0-9]+]], [[WS]]109; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_u_w_RES)110; CHECK-DAG: st.w [[WD]], 0([[R2]])111; CHECK: .size llvm_mips_ftrunc_u_w_test112;113@llvm_mips_ftrunc_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16114@llvm_mips_ftrunc_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16115 116define void @llvm_mips_ftrunc_u_d_test() nounwind {117entry:118 %0 = load <2 x double>, ptr @llvm_mips_ftrunc_u_d_ARG1119 %1 = tail call <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double> %0)120 store <2 x i64> %1, ptr @llvm_mips_ftrunc_u_d_RES121 ret void122}123 124declare <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double>) nounwind125 126; CHECK: llvm_mips_ftrunc_u_d_test:127; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftrunc_u_d_ARG1)128; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])129; CHECK-DAG: ftrunc_u.d [[WD:\$w[0-9]+]], [[WS]]130; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftrunc_u_d_RES)131; CHECK-DAG: st.d [[WD]], 0([[R2]])132; CHECK: .size llvm_mips_ftrunc_u_d_test133;134@llvm_mips_ftint_s_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16135@llvm_mips_ftint_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16136 137define void @llvm_mips_ftint_s_w_test() nounwind {138entry:139 %0 = load <4 x float>, ptr @llvm_mips_ftint_s_w_ARG1140 %1 = tail call <4 x i32> @llvm.mips.ftint.s.w(<4 x float> %0)141 store <4 x i32> %1, ptr @llvm_mips_ftint_s_w_RES142 ret void143}144 145declare <4 x i32> @llvm.mips.ftint.s.w(<4 x float>) nounwind146 147; CHECK: llvm_mips_ftint_s_w_test:148; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_s_w_ARG1)149; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])150; CHECK-DAG: ftint_s.w [[WD:\$w[0-9]+]], [[WS]]151; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_s_w_RES)152; CHECK-DAG: st.w [[WD]], 0([[R2]])153; CHECK: .size llvm_mips_ftint_s_w_test154;155@llvm_mips_ftint_s_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16156@llvm_mips_ftint_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16157 158define void @llvm_mips_ftint_s_d_test() nounwind {159entry:160 %0 = load <2 x double>, ptr @llvm_mips_ftint_s_d_ARG1161 %1 = tail call <2 x i64> @llvm.mips.ftint.s.d(<2 x double> %0)162 store <2 x i64> %1, ptr @llvm_mips_ftint_s_d_RES163 ret void164}165 166declare <2 x i64> @llvm.mips.ftint.s.d(<2 x double>) nounwind167 168; CHECK: llvm_mips_ftint_s_d_test:169; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_s_d_ARG1)170; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])171; CHECK-DAG: ftint_s.d [[WD:\$w[0-9]+]], [[WS]]172; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_s_d_RES)173; CHECK-DAG: st.d [[WD]], 0([[R2]])174; CHECK: .size llvm_mips_ftint_s_d_test175;176@llvm_mips_ftint_u_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16177@llvm_mips_ftint_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16178 179define void @llvm_mips_ftint_u_w_test() nounwind {180entry:181 %0 = load <4 x float>, ptr @llvm_mips_ftint_u_w_ARG1182 %1 = tail call <4 x i32> @llvm.mips.ftint.u.w(<4 x float> %0)183 store <4 x i32> %1, ptr @llvm_mips_ftint_u_w_RES184 ret void185}186 187declare <4 x i32> @llvm.mips.ftint.u.w(<4 x float>) nounwind188 189; CHECK: llvm_mips_ftint_u_w_test:190; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_u_w_ARG1)191; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])192; CHECK-DAG: ftint_u.w [[WD:\$w[0-9]+]], [[WS]]193; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_u_w_RES)194; CHECK-DAG: st.w [[WD]], 0([[R2]])195; CHECK: .size llvm_mips_ftint_u_w_test196;197@llvm_mips_ftint_u_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16198@llvm_mips_ftint_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16199 200define void @llvm_mips_ftint_u_d_test() nounwind {201entry:202 %0 = load <2 x double>, ptr @llvm_mips_ftint_u_d_ARG1203 %1 = tail call <2 x i64> @llvm.mips.ftint.u.d(<2 x double> %0)204 store <2 x i64> %1, ptr @llvm_mips_ftint_u_d_RES205 ret void206}207 208declare <2 x i64> @llvm.mips.ftint.u.d(<2 x double>) nounwind209 210; CHECK: llvm_mips_ftint_u_d_test:211; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ftint_u_d_ARG1)212; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])213; CHECK-DAG: ftint_u.d [[WD:\$w[0-9]+]], [[WS]]214; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ftint_u_d_RES)215; CHECK-DAG: st.d [[WD]], 0([[R2]])216; CHECK: .size llvm_mips_ftint_u_d_test217;218